ml605, v134, timer interrupt

#include "xtmrctr_l.h"
#include "xintc_l.h"
#include "xparameters.h"
#include "xil_macroback.h"
#include "xbasic_types.h"

/*

void ext1_handler(void * baseaddr_p)
{
 Xint32 baseaddr = (int)baseaddr_p;
 xil_printf("x");
}
*/

void timer_handler(void *baseaddr_p)
{
 int baseaddr = (int)baseaddr_p;
 unsigned int csr;

 csr = XTmrCtr_mGetControlStatusReg(XPAR_AXI_TIMER_0_BASEADDR, 0);
   xil_printf("a");
 XTmrCtr_mSetControlStatusReg(XPAR_AXI_TIMER_0_BASEADDR, 0, csr);
}

int main()
{
 XIntc_mMasterEnable(XPAR_MICROBLAZE_0_INTC_BASEADDR);

   XIntc_mEnableIntr(XPAR_MICROBLAZE_0_INTC_BASEADDR ,
      //XPAR_SYSTEM_EXT_INT_MASK |
      XPAR_AXI_TIMER_0_INTERRUPT_MASK);
   /*
 XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
       XPAR_XPS_INTC_0_SYSTEM_EXT_INT_INTR,
       ext1_handler,
       NULL);
*/
 XIntc_RegisterHandler(XPAR_MICROBLAZE_0_INTC_BASEADDR,
       XPAR_MICROBLAZE_0_INTC_AXI_TIMER_0_INTERRUPT_INTR,
       timer_handler,
       XPAR_AXI_TIMER_0_BASEADDR);

 XTmrCtr_mSetLoadReg(XPAR_AXI_TIMER_0_BASEADDR,
        0,
        100000000);
 XTmrCtr_mSetControlStatusReg(XPAR_AXI_TIMER_0_BASEADDR,
         0,
         XTC_CSR_INT_OCCURED_MASK |
         XTC_CSR_LOAD_MASK );

 XTmrCtr_mSetControlStatusReg(XPAR_AXI_TIMER_0_BASEADDR,
         0,
         XTC_CSR_ENABLE_TMR_MASK |
         XTC_CSR_ENABLE_INT_MASK |
         XTC_CSR_AUTO_RELOAD_MASK |
         XTC_CSR_DOWN_COUNT_MASK);
   microblaze_enable_interrupts();
   while (1);
}