sw_npi.zip


top.vhd


system.mhs


system.xmp


v144_z702_npi_v400b - 복사본.zip


'edk > npi' 카테고리의 다른 글

npi_v4_00_b, latency를 줄인 버전, z702, ise 14.4  (0) 2013.07.02
npi_v4_00_b, latency를 줄인 버전, kc705, ise 14.4  (2) 2013.07.01
axi master design file  (0) 2013.03.12
axi npi  (1) 2012.06.03
axi npi  (0) 2012.04.28
NPI에 대하여  (0) 2011.11.16
by Real Xilinx ... xilinx 2013. 7. 2. 17:35




sw_npi_v400b.zip



axi_user_npi_v4_00_b.zip


top.vhd


tb_bench.vhd


system.xml



ddr3_model.v




v144_kc705_npi_v400b_mp4.vol1.egg


v144_kc705_npi_v400b_mp4.vol2.egg


v144_kc705_npi_v400b_mp4.vol3.egg


v144_kc705_npi_v400b_mp4.vol4.egg


v144_kc705_npi_v400b_mp4.vol5.egg



'edk > npi' 카테고리의 다른 글

npi_v4_00_b, latency를 줄인 버전, z702, ise 14.4  (0) 2013.07.02
npi_v4_00_b, latency를 줄인 버전, kc705, ise 14.4  (2) 2013.07.01
axi master design file  (0) 2013.03.12
axi npi  (1) 2012.06.03
axi npi  (0) 2012.04.28
NPI에 대하여  (0) 2011.11.16
by Real Xilinx ... xilinx 2013. 7. 1. 08:17
  • 올제텍.김승용 2013.07.09 18:52 ADDR EDIT/DEL REPLY

    안녕하세요
    제가 동영상 보면서 좀 따라 해보려구 하는데
    화질이 너무 안 좋아요~
    올려놓으신 영상 압축 파일도 풀면 48MB 맞나요?
    이것도 화질 똑같은데요.
    타이핑 하시는 거도 글자가 보이지 않습니다. ㅜㅜ
    원본 영상 따로 보내주실 수 있을까요??
    idissy@naver.com 입니다.
    유용한 정보 감사드립니다.

  • ㄱㅎ 2013.07.21 00:31 ADDR EDIT/DEL REPLY

    노트북을 읽어버려서 원 영상을 찾을 수 없어서요...곧 새로운 버전으로 준비해 드릴께요

    문의사항은 hyuk.kim@xilinx.com 으로 보내 주세요.

by Real Xilinx ... xilinx 2013. 3. 12. 16:05

axi npi

 

axi_npi_mp4.vol1.egg

 

axi_npi_mp4.vol2.egg

 

axi_npi_mp4.vol3.egg

 

axi_user_npi_v3_03_d.zip

 

main.c

 

'edk > npi' 카테고리의 다른 글

npi_v4_00_b, latency를 줄인 버전, kc705, ise 14.4  (2) 2013.07.01
axi master design file  (0) 2013.03.12
axi npi  (1) 2012.06.03
axi npi  (0) 2012.04.28
NPI에 대하여  (0) 2011.11.16
NPI를 구성하는 파일들....  (0) 2011.11.16
by Real Xilinx ... xilinx 2012. 6. 3. 00:21
  • jhpark 2012.12.20 17:08 ADDR EDIT/DEL REPLY


    위의 ip로 zynq에서 test해 보았더니 ip 추가가 되질 않습니다.
    혹시 zynq 보드에서 사용할 수 있는 방법이 있는지 궁금합니다.

axi npi

sp601보드용

 

-------------------------------------------------------------------------------
-- system_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity system_top is
  port (
    zio : inout std_logic;
    rzq : inout std_logic;
    mcbx_dram_we_n : out std_logic;
    mcbx_dram_udqs_n : inout std_logic;
    mcbx_dram_udqs : inout std_logic;
    mcbx_dram_udm : out std_logic;
    mcbx_dram_ras_n : out std_logic;
    mcbx_dram_odt : out std_logic;
    mcbx_dram_ldm : out std_logic;
    mcbx_dram_dqs_n : inout std_logic;
    mcbx_dram_dqs : inout std_logic;
    mcbx_dram_dq : inout std_logic_vector(15 downto 0);
    mcbx_dram_ddr3_rst : out std_logic;
    mcbx_dram_clk_n : out std_logic;
    mcbx_dram_clk : out std_logic;
    mcbx_dram_cke : out std_logic;
    mcbx_dram_cas_n : out std_logic;
    mcbx_dram_ba : out std_logic_vector(2 downto 0);
    mcbx_dram_addr : out std_logic_vector(12 downto 0);
    RS232_Uart_1_sout : out std_logic;
    RS232_Uart_1_sin : in std_logic;
    RESET : in std_logic;
    LEDs_4Bits_TRI_O : out std_logic_vector(3 downto 0);
    CLK_P : in std_logic;
    CLK_N : in std_logic
  );
end system_top;

architecture STRUCTURE of system_top is

  component system is
    port (
      zio : inout std_logic;
      rzq : inout std_logic;
      mcbx_dram_we_n : out std_logic;
      mcbx_dram_udqs_n : inout std_logic;
      mcbx_dram_udqs : inout std_logic;
      mcbx_dram_udm : out std_logic;
      mcbx_dram_ras_n : out std_logic;
      mcbx_dram_odt : out std_logic;
      mcbx_dram_ldm : out std_logic;
      mcbx_dram_dqs_n : inout std_logic;
      mcbx_dram_dqs : inout std_logic;
      mcbx_dram_dq : inout std_logic_vector(15 downto 0);
      mcbx_dram_ddr3_rst : out std_logic;
      mcbx_dram_clk_n : out std_logic;
      mcbx_dram_clk : out std_logic;
      mcbx_dram_cke : out std_logic;
      mcbx_dram_cas_n : out std_logic;
      mcbx_dram_ba : out std_logic_vector(2 downto 0);
      mcbx_dram_addr : out std_logic_vector(12 downto 0);
      RS232_Uart_1_sout : out std_logic;
      RS232_Uart_1_sin : in std_logic;
      RESET : in std_logic;
      LEDs_4Bits_TRI_O : out std_logic_vector(3 downto 0);
      CLK_P : in std_logic;
      CLK_N : in std_logic;
      clk_out : out std_logic;
      wr_fifo_full : out std_logic;
      npi_wr_ready : out std_logic;
      wr_fifo_wr_en : in std_logic;
      wr_fifo_data : in std_logic_vector(31 downto 0);
      npi_rd_ready : out std_logic;
      wr_fifo_clk : in std_logic;
      rd_fifo_full : out std_logic;
      rd_fifo_clk : in std_logic;
      rd_fifo_rd_en : in std_logic;
      rd_fifo_data : out std_logic_vector(31 downto 0);
      rd_fifo_empty : out std_logic;
      wr_fifo_empty : out std_logic
    );
  end component;

  attribute BOX_TYPE : STRING;
  attribute BOX_TYPE of system : component is "user_black_box";

  signal npi_rd_ready : std_logic;
  signal npi_wr_ready : std_logic;
  signal rd_fifo_clk : std_logic;
  signal rd_fifo_data : std_logic_vector(31 downto 0);
  signal rd_fifo_empty : std_logic;
  signal rd_fifo_full : std_logic;
  signal rd_fifo_rd_en : std_logic;
  signal wr_fifo_clk : std_logic;
  signal wr_fifo_data : std_logic_vector(31 downto 0);
  signal wr_fifo_empty : std_logic;
  signal wr_fifo_full : std_logic;
  signal not_wr_fifo_full, not_rd_fifo_empty, wr_fifo_wr_en  : std_logic;
  signal clk : std_logic;
  signal wr_fifo_cnt : std_logic_vector(31 downto 0); 
  signal temp0 : std_logic_vector(15 downto 0); 
  signal temp1 : std_logic_vector(7 downto 0); 

begin

  system_i : system
    port map (
      zio => zio,
      rzq => rzq,
      mcbx_dram_we_n => mcbx_dram_we_n,
      mcbx_dram_udqs_n => mcbx_dram_udqs_n,
      mcbx_dram_udqs => mcbx_dram_udqs,
      mcbx_dram_udm => mcbx_dram_udm,
      mcbx_dram_ras_n => mcbx_dram_ras_n,
      mcbx_dram_odt => mcbx_dram_odt,
      mcbx_dram_ldm => mcbx_dram_ldm,
      mcbx_dram_dqs_n => mcbx_dram_dqs_n,
      mcbx_dram_dqs => mcbx_dram_dqs,
      mcbx_dram_dq => mcbx_dram_dq,
      mcbx_dram_ddr3_rst => mcbx_dram_ddr3_rst,
      mcbx_dram_clk_n => mcbx_dram_clk_n,
      mcbx_dram_clk => mcbx_dram_clk,
      mcbx_dram_cke => mcbx_dram_cke,
      mcbx_dram_cas_n => mcbx_dram_cas_n,
      mcbx_dram_ba => mcbx_dram_ba,
      mcbx_dram_addr => mcbx_dram_addr,
      RS232_Uart_1_sout => RS232_Uart_1_sout,
      RS232_Uart_1_sin => RS232_Uart_1_sin,
      RESET => RESET,
      LEDs_4Bits_TRI_O => open,
      CLK_P => CLK_P,
      CLK_N => CLK_N,
      clk_out => clk,
      wr_fifo_full => wr_fifo_full,
      npi_wr_ready => npi_wr_ready,
      wr_fifo_wr_en => wr_fifo_wr_en,
      wr_fifo_data => wr_fifo_data,
      npi_rd_ready => npi_rd_ready,
      wr_fifo_clk => wr_fifo_clk,
      rd_fifo_full => rd_fifo_full,
      rd_fifo_clk => rd_fifo_clk,
      rd_fifo_rd_en => rd_fifo_rd_en,
      rd_fifo_data => rd_fifo_data,
      rd_fifo_empty => rd_fifo_empty,
      wr_fifo_empty => wr_fifo_empty
    );

 wr_fifo_clk <= clk;
 rd_fifo_clk <= clk;
 wr_fifo_data <= wr_fifo_cnt;

 process(wr_fifo_clk)
 begin
  if wr_fifo_clk'event and wr_fifo_clk = '1' then
   if npi_wr_ready = '0' then
      wr_fifo_cnt <= x"00000001";
   else
    if wr_fifo_full = '0' then
     wr_fifo_cnt <= wr_fifo_cnt + 1;
    end if;
   end if;
  end if;
 end process;

 process(rd_fifo_clk)
 begin
  if rd_fifo_clk'event and rd_fifo_clk = '1' then
   temp0 <= rd_fifo_data(31 downto 16) and rd_fifo_data(15 downto 0);
   temp1 <= temp0(15 downto 8) and temp0(7 downto 0);
   LEDs_4Bits_TRI_O <= temp1(7 downto 4) and temp1(3 downto 0);
  end if;
 end process;

 -----
 wr_fifo_wr_en <= not_wr_fifo_full and npi_wr_ready;
 rd_fifo_rd_en <= npi_rd_ready and not_rd_fifo_empty;
 -----
 not_rd_fifo_empty <= rd_fifo_empty;
 not_wr_fifo_full <= not wr_fifo_full;
end architecture STRUCTURE;

 

 

user_logic.vhd

 

------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.            **
-- **                                                                       **
-- ** Xilinx, Inc.                                                          **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
-- ** FOR A PARTICULAR PURPOSE.                                             **
-- **                                                                       **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename:          user_logic.vhd
-- Version:           1.00.a
-- Description:       User logic.
-- Date:              Wed Apr 04 10:57:23 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard:     VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
--   active low signals:                    "*_n"
--   clock signals:                         "clk", "clk_div#", "clk_#x"
--   reset signals:                         "rst", "rst_n"
--   generics:                              "C_*"
--   user defined types:                    "*_TYPE"
--   state machine next state:              "*_ns"
--   state machine current state:           "*_cs"
--   combinatorial signals:                 "*_com"
--   pipelined or register delay signals:   "*_d#"
--   counter signals:                       "*cnt*"
--   clock enable signals:                  "*_ce"
--   internal version of output port:       "*_i"
--   device pins:                           "*_pin"
--   ports:                                 "- Names begin with Uppercase"
--   processes:                             "*_PROCESS"
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------

-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.srl_fifo_f;

Library UNISIM;
use UNISIM.vcomponents.all;

Library UNIMACRO;
use UNIMACRO.vcomponents.all;

-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
--   C_MST_NATIVE_DATA_WIDTH      -- Internal bus width on user-side
--   C_LENGTH_WIDTH               -- Master interface data bus width
--   C_MST_AWIDTH                 -- Master-Intf address bus width
--   C_NUM_REG                    -- Number of software accessible registers
--   C_SLV_DWIDTH                 -- Slave interface data bus width
--
-- Definition of Ports:
--   Bus2IP_Clk                   -- Bus to IP clock
--   Bus2IP_Resetn                -- Bus to IP reset
--   Bus2IP_Data                  -- Bus to IP data bus
--   Bus2IP_BE                    -- Bus to IP byte enables
--   Bus2IP_RdCE                  -- Bus to IP read chip enable
--   Bus2IP_WrCE                  -- Bus to IP write chip enable
--   IP2Bus_Data                  -- IP to Bus data bus
--   IP2Bus_RdAck                 -- IP to Bus read transfer acknowledgement
--   IP2Bus_WrAck                 -- IP to Bus write transfer acknowledgement
--   IP2Bus_Error                 -- IP to Bus error response
--   ip2bus_mstrd_req             -- IP to Bus master read request
--   ip2bus_mstwr_req             -- IP to Bus master write request
--   ip2bus_mst_addr              -- IP to Bus master read/write address
--   ip2bus_mst_be                -- IP to Bus byte enable
--   ip2bus_mst_length            -- Ip to Bus master transfer length
--   ip2bus_mst_type              -- Ip to Bus burst assertion control
--   ip2bus_mst_lock              -- Ip to Bus bus lock
--   ip2bus_mst_reset             -- Ip to Bus master reset
--   bus2ip_mst_cmdack            -- Bus to Ip master command ack
--   bus2ip_mst_cmplt             -- Bus to Ip master trans complete
--   bus2ip_mst_error             -- Bus to Ip master error
--   bus2ip_mst_rearbitrate       -- Bus to Ip master re-arbitrate for bus ownership
--   bus2ip_mst_cmd_timeout       -- Bus to Ip master command time out
--   bus2ip_mstrd_d               -- Bus to Ip master read data
--   bus2ip_mstrd_rem             -- Bus to Ip master read data rem
--   bus2ip_mstrd_sof_n           -- Bus to Ip master read start of frame
--   bus2ip_mstrd_eof_n           -- Bus to Ip master read end of frame
--   bus2ip_mstrd_src_rdy_n       -- Bus to Ip master read source ready
--   bus2ip_mstrd_src_dsc_n       -- Bus to Ip master read source dsc
--   ip2bus_mstrd_dst_rdy_n       -- Ip to Bus master read dest. ready
--   ip2bus_mstrd_dst_dsc_n       -- Ip to Bus master read dest. dsc
--   ip2bus_mstwr_d               -- Ip to Bus master write data
--   ip2bus_mstwr_rem             -- Ip to Bus master write data rem
--   ip2bus_mstwr_src_rdy_n       -- Ip to Bus master write source ready
--   ip2bus_mstwr_src_dsc_n       -- Ip to Bus master write source dsc
--   ip2bus_mstwr_sof_n           -- Ip to Bus master write start of frame
--   ip2bus_mstwr_eof_n           -- Ip to Bus master write end of frame
--   bus2ip_mstwr_dst_rdy_n       -- Bus to Ip master write dest. ready
--   bus2ip_mstwr_dst_dsc_n       -- Bus to Ip master write dest. ready
------------------------------------------------------------------------------

entity user_logic is
 generic
 (
  -- ADD USER GENERICS BELOW THIS LINE ---------------
  --USER generics added here
  -- ADD USER GENERICS ABOVE THIS LINE ---------------

  -- DO NOT EDIT BELOW THIS LINE ---------------------
  -- Bus protocol parameters, do not add to or delete
  C_MST_NATIVE_DATA_WIDTH        : integer              := 32;
  C_LENGTH_WIDTH                 : integer              := 12;
  C_MST_AWIDTH                   : integer              := 32;
  C_NUM_REG                      : integer              := 12;
  C_SLV_DWIDTH                   : integer              := 32
 -- DO NOT EDIT ABOVE THIS LINE ---------------------
 );
 port
 (
  -- ADD USER PORTS BELOW THIS LINE ------------------
  --USER ports added here
  -- ADD USER PORTS ABOVE THIS LINE ------------------
  rd_fifo_clk               : in std_logic;
  rd_fifo_rd_en             : in std_logic;
  rd_fifo_data              : out std_logic_vector(31 downto 0);
  rd_fifo_empty             : out std_logic;
  rd_fifo_full              : out std_logic;
  npi_rd_ready              : out std_logic;
  ----------------------------------------------------
  wr_fifo_clk               : in std_logic;
  wr_fifo_wr_en             : in std_logic;
  wr_fifo_data              : in std_logic_vector(31 downto 0);
  wr_fifo_empty             : out std_logic;
  wr_fifo_full              : out std_logic;
  npi_wr_ready              : out std_logic;

  -- DO NOT EDIT BELOW THIS LINE ---------------------
  -- Bus protocol ports, do not add to or delete
  Bus2IP_Clk                     : in  std_logic;
  Bus2IP_Resetn                  : in  std_logic;
  Bus2IP_Data                    : in  std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  Bus2IP_BE                      : in  std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
  Bus2IP_RdCE                    : in  std_logic_vector(C_NUM_REG-1 downto 0);
  Bus2IP_WrCE                    : in  std_logic_vector(C_NUM_REG-1 downto 0);
  IP2Bus_Data                    : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  IP2Bus_RdAck                   : out std_logic;
  IP2Bus_WrAck                   : out std_logic;
  IP2Bus_Error                   : out std_logic;
  ip2bus_mstrd_req               : out std_logic;
  ip2bus_mstwr_req               : out std_logic;
  ip2bus_mst_addr                : out std_logic_vector(C_MST_AWIDTH-1 downto 0);
  ip2bus_mst_be                  : out std_logic_vector((C_MST_NATIVE_DATA_WIDTH/8)-1 downto 0);
  ip2bus_mst_length              : out std_logic_vector(C_LENGTH_WIDTH-1 downto 0);
  ip2bus_mst_type                : out std_logic;
  ip2bus_mst_lock                : out std_logic;
  ip2bus_mst_reset               : out std_logic;
  bus2ip_mst_cmdack              : in  std_logic;
  bus2ip_mst_cmplt               : in  std_logic;
  bus2ip_mst_error               : in  std_logic;
  bus2ip_mst_rearbitrate         : in  std_logic;
  bus2ip_mst_cmd_timeout         : in  std_logic;
  bus2ip_mstrd_d                 : in  std_logic_vector(C_MST_NATIVE_DATA_WIDTH-1 downto 0);
  bus2ip_mstrd_rem               : in  std_logic_vector((C_MST_NATIVE_DATA_WIDTH)/8-1 downto 0);
  bus2ip_mstrd_sof_n             : in  std_logic;
  bus2ip_mstrd_eof_n             : in  std_logic;
  bus2ip_mstrd_src_rdy_n         : in  std_logic;
  bus2ip_mstrd_src_dsc_n         : in  std_logic;
  ip2bus_mstrd_dst_rdy_n         : out std_logic;
  ip2bus_mstrd_dst_dsc_n         : out std_logic;
  ip2bus_mstwr_d                 : out std_logic_vector(C_MST_NATIVE_DATA_WIDTH-1 downto 0);
  ip2bus_mstwr_rem               : out std_logic_vector((C_MST_NATIVE_DATA_WIDTH)/8-1 downto 0);
  ip2bus_mstwr_src_rdy_n         : out std_logic;
  ip2bus_mstwr_src_dsc_n         : out std_logic;
  ip2bus_mstwr_sof_n             : out std_logic;
  ip2bus_mstwr_eof_n             : out std_logic;
  bus2ip_mstwr_dst_rdy_n         : in  std_logic;
  bus2ip_mstwr_dst_dsc_n         : in  std_logic
 -- DO NOT EDIT ABOVE THIS LINE ---------------------
 );

 attribute MAX_FANOUT : string;
 attribute SIGIS : string;

 attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
 attribute SIGIS of Bus2IP_Resetn : signal is "RST";
 attribute SIGIS of ip2bus_mst_reset: signal is "RST";

end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is
 COMPONENT afifo_s6_32x64
  PORT (
     rst : IN STD_LOGIC;
     wr_clk : IN STD_LOGIC;
     rd_clk : IN STD_LOGIC;
     din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
     wr_en : IN STD_LOGIC;
     rd_en : IN STD_LOGIC;
     dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
     full : OUT STD_LOGIC;
     empty : OUT STD_LOGIC
    );
 END COMPONENT;

 COMPONENT afifo_v6_32x64
  PORT (
     rst : IN STD_LOGIC;
     wr_clk : IN STD_LOGIC;
     rd_clk : IN STD_LOGIC;
     din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
     wr_en : IN STD_LOGIC;
     rd_en : IN STD_LOGIC;
     dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
     full : OUT STD_LOGIC;
     empty : OUT STD_LOGIC
    );
 END COMPONENT;
 
  COMPONENT afifo_k7_32x64
  PORT (
     rst : IN STD_LOGIC;
     wr_clk : IN STD_LOGIC;
     rd_clk : IN STD_LOGIC;
     din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
     wr_en : IN STD_LOGIC;
     rd_en : IN STD_LOGIC;
     dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
     full : OUT STD_LOGIC;
     empty : OUT STD_LOGIC
    );
 END COMPONENT;

 constant start_wr_cmd_patt : std_logic_vector(7 downto 0) := X"66"; 
 constant start_rd_cmd_patt : std_logic_vector(7 downto 0) := X"55";
 constant user_rst_cmd_patt : std_logic_vector(7 downto 0) := X"9A";
---------------
 type st_m_type is (st_fifo_rst3clk, st_idle, st_wait_cmd, st_rd_wait_rdy , st_rd_ack,  st_wait_for_data, st_rd_finish, st_wr_wait_rdy, st_wr_ack, st0, st00, st1, st3, st4, st_done);
 signal st_m : st_m_type;
---------------
 signal slv_reg_write_sel              : std_logic_vector(7 downto 0);
 signal slv_reg_read_sel               : std_logic_vector(7 downto 0);
 signal slv_ip2bus_data                : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
 signal slv_read_ack                   : std_logic;
 signal slv_write_ack                  : std_logic;
 signal start_wr_cmd, start_rd_cmd, user_rst_cmd : std_logic;
 signal not_bus2ip_mstrd_src_rdy_n : std_logic;
 signal addra : std_logic_vector(12 downto 0);
 signal data_cnt: std_logic_vector(31 downto 0);
 signal cnt_mst_cmd_sm_set_error : std_logic_vector(15 downto 0) := (others => '0');
 signal cnt_mst_cmd_sm_set_timeout : std_logic_vector(15 downto 0) := (others => '0');
 signal cnt_16bits : std_logic_vector(3 downto 0);
 signal add_lut_src : std_logic_vector(7 downto 0);
 signal cnt_fifo_rst3clk : std_logic_vector(3 downto 0);
 signal wr_fifo_full_s : std_logic;
 signal add_cnt, global_cnt  : std_logic_vector(15 downto 0);
 signal fifo_rst, wr_fifo_rd_en, not_bus2ip_mstwr_dst_rdy_n  : std_logic;
 signal rd_fifo_empty_s, rd_fifo_full_s : std_logic;
 signal c_burst_repeat_cnt : std_logic_vector(15 downto 0);
 signal sm_status : std_logic_vector(7 downto 0) := x"00";
 signal c_global_cnt       : std_logic_vector(15 downto 0);
 signal Bus2IP_Reset                   : std_logic;
 attribute SIGIS of Bus2IP_Reset   : signal is "RST";


begin
 process(bus2ip_clk)
 begin
  if bus2ip_clk'event and bus2ip_clk = '1' then
   if bus2ip_resetn = '0' or user_rst_cmd = '1' then
    ip2bus_mstrd_req  <= '0';
    ip2bus_mst_be <= x"0";
    ip2bus_mstwr_rem  <= x"f";
    ip2bus_mst_type <= '0';
    ip2bus_mst_lock  <= '0';
    ip2bus_mst_reset <= '0'; 
    ip2bus_mst_length <= (others => '0');
    ip2bus_mstwr_sof_n <= '1';
    ip2bus_mstwr_eof_n <= '1';
    cnt_fifo_rst3clk <= (others => '0');
    npi_wr_ready <= '0';             
    npi_rd_ready <= '0';            
    st_m <= st_fifo_rst3clk;
   else
    case st_m is
     when st_fifo_rst3clk =>
      sm_status <= x"01";
      fifo_rst <= '1';
      cnt_fifo_rst3clk <= cnt_fifo_rst3clk + 1;
      if(cnt_fifo_rst3clk = x"a") then
       st_m <= st_idle;
      end if;
     when st_idle =>
      sm_status <= x"02";
      global_cnt <= (others => '0');
      add_cnt <= (others => '0');
      npi_wr_ready <= '0';             
      npi_rd_ready <= '0';            
      fifo_rst <= '0';
      if(wr_fifo_full_s = '0' and rd_fifo_full_s = '0' ) then
       st_m <= st_wait_cmd;
      end if;
     when st_wait_cmd =>
      sm_status <= x"03";
      if start_rd_cmd = '1' then
       npi_rd_ready <= '1';             
       st_m <= st_rd_wait_rdy;
      elsif start_wr_cmd = '1' then
       npi_wr_ready <= '1';             
       st_m <= st_wr_wait_rdy;
      end if;
     ----------------------------------------------------------------
     ---- start read from memory
     ----------------------------------------------------------------
     when st_rd_wait_rdy =>
      sm_status <= x"04";
      ip2bus_mstrd_req <= '1';
      ip2bus_mst_addr <= add_lut_src & "00" & add_cnt & "000000"; -- npi use 16x32bits*add_cnt 16*4byte == 0x40 ==> 0b0100_0000
      ip2bus_mst_length <= x"00040";
      ip2bus_mst_be <= x"f";
      ip2bus_mst_type <= '1';
      st_m <= st_rd_ack;
     when st_rd_ack =>
      sm_status <= x"05";
      if bus2ip_mst_cmdack = '1' and bus2ip_mst_cmplt = '0' then             
       ip2bus_mstrd_req <= '0';
       ip2bus_mst_type <= '0';
       st_m <= st_wait_for_data;
      elsif bus2ip_mst_cmplt = '1' then
       st_m <= st_done;
       if bus2ip_mst_cmd_timeout = '1' then
        cnt_mst_cmd_sm_set_error <= cnt_mst_cmd_sm_set_error + 1;
        cnt_mst_cmd_sm_set_timeout <= cnt_mst_cmd_sm_set_timeout + 1;
       elsif bus2ip_mst_error = '1' then
        cnt_mst_cmd_sm_set_error <= cnt_mst_cmd_sm_set_error + 1;
       end if;
      end if;
     when st_wait_for_data =>
      sm_status <= x"06";
      if bus2ip_mst_cmplt = '1' then
       st_m <= st_done;
       add_cnt <= add_cnt + 1;
       if c_burst_repeat_cnt = (add_cnt + 1) then
        global_cnt <= global_cnt + 1; 
        if (c_global_cnt = global_cnt + 1) then
         st_m <= st_rd_finish;
        else
         add_cnt <= (others => '0');
         st_m <= st_rd_wait_rdy;
        end if;
       end if;

       if bus2ip_mst_cmd_timeout = '1' then
        cnt_mst_cmd_sm_set_error <= cnt_mst_cmd_sm_set_error + 1;
        cnt_mst_cmd_sm_set_timeout <= cnt_mst_cmd_sm_set_timeout + 1;
       elsif bus2ip_mst_error = '1' then
        cnt_mst_cmd_sm_set_error <= cnt_mst_cmd_sm_set_error + 1;
       end if;
      end if;
     when st_rd_finish =>
      sm_status <= x"07";
      if rd_fifo_empty_s = '1' then
       fifo_rst <= '1';
       cnt_fifo_rst3clk <= (others => '0');
       st_m <= st_fifo_rst3clk;
      end if;
     ----------------------------------------------------------------
     ---- start write from memory
     ----------------------------------------------------------------
     when st_wr_wait_rdy =>
      sm_status <= x"08";
      ip2bus_mstwr_req <= '1';
      ip2bus_mst_addr <= add_lut_src & "00" & add_cnt & "000000";
      ip2bus_mst_length <= x"00040";
      ip2bus_mst_be <= x"f";
      ip2bus_mst_type <= '1';
      cnt_16bits <= (others => '0');
      st_m <= st_wr_ack;
     when st_wr_ack =>
      sm_status <= x"09";
      if bus2ip_mst_cmdack = '1' and bus2ip_mst_cmplt = '0' then             
       ip2bus_mstwr_src_rdy_n <= '0';
       ip2bus_mstwr_req <= '0';
       ip2bus_mst_type <= '0';
       st_m <= st00;
      end if;
     when st00 =>
      sm_status <= x"0a";
      st_m <= st0;
     when st0 =>
      if bus2ip_mstwr_dst_rdy_n = '0' then      
       cnt_16bits <= cnt_16bits + 1; 
       ip2bus_mstwr_sof_n <= '1';
       st_m <= st1;
      end if;
     when st1 =>
      sm_status <= x"0b";
      if bus2ip_mstwr_dst_rdy_n = '0' then      
       cnt_16bits <= cnt_16bits + 1; 
       if cnt_16bits = x"f" then
        ip2bus_mstwr_eof_n <= '0';
        st_m <= st3;
       end if;
      end if;
     when st3 =>
      sm_status <= x"0c";
      if bus2ip_mstwr_dst_rdy_n = '0' then      
       ip2bus_mstwr_src_rdy_n <= '1';
       ip2bus_mstwr_eof_n <= '1';
       st_m <= st4;
      end if;
     when st4 =>
      sm_status <= x"0d";
      if bus2ip_mst_cmplt = '1' then
       add_cnt <= add_cnt + 1;
       if c_burst_repeat_cnt = add_cnt then
        global_cnt <= global_cnt + 1;
        if c_global_cnt = global_cnt + 1 then
         fifo_rst <= '1';
         cnt_fifo_rst3clk <= (others => '0');
         st_m <= st_fifo_rst3clk;
        else
         add_cnt <= (others => '0');
         st_m <= st_wr_wait_rdy;
        end if;
       end if;
      else
       st_m <= st_idle;
      end if;
     when others =>
      st_m <= st_idle;
    end case;
   end if;
  end if;
 end process;

 not_bus2ip_mstrd_src_rdy_n <= (not bus2ip_mstrd_src_rdy_n);

 rd_fifo_from_bus : afifo_s6_32x64
 PORT MAP (
     rst => fifo_rst,
     ---
     wr_clk => Bus2IP_Clk,
     wr_en => not_bus2ip_mstrd_src_rdy_n,
     din => Bus2IP_MstRd_d,
     ---
     rd_clk => rd_fifo_clk,
     rd_en => rd_fifo_rd_en,
     dout => rd_fifo_data,
     ---
     full => ip2bus_mstrd_dst_rdy_n,
     empty => rd_fifo_empty
    );

 not_bus2ip_mstwr_dst_rdy_n <= not bus2ip_mstwr_dst_rdy_n;
 wr_fifo_rd_en<= '1' when st_m = st00 else not_bus2ip_mstwr_dst_rdy_n;

 wr_fifo_from_bus : afifo_s6_32x64
 PORT MAP (
     rst => fifo_rst,
     ---
     wr_clk => wr_fifo_clk,
     wr_en => wr_fifo_wr_en ,
     din => wr_fifo_data,
     ----
     rd_clk => Bus2IP_Clk,
     rd_en => wr_fifo_rd_en,
     dout => ip2bus_mstwr_d,
     ---
     full => wr_fifo_full_s,
     empty => wr_fifo_empty
    );

 slv_reg_write_sel <= Bus2IP_WrCE(7 downto 0);
 slv_reg_read_sel  <= Bus2IP_RdCE(7 downto 0);
 slv_write_ack     <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7);
 slv_read_ack      <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7);


 ip2bus_data  <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');
 Bus2IP_Reset   <= not (Bus2IP_Resetn);


 IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');

 IP2Bus_WrAck <= slv_write_ack;
 IP2Bus_RdAck <= slv_read_ack;

 IP2Bus_Error <= '0';
 ----------------------------------------------------------------------------------------------------------------------------------------------
 -- command flag
 ----------------------------------------------------------------------------------------------------------------------------------------------
 process( Bus2IP_Clk ) is
 begin
  if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
   if Bus2IP_Resetn = '0' then
    add_lut_src <= (others => '0');
    c_burst_repeat_cnt <= (others => '0');
    c_global_cnt <= (others => '0');
   else
    case slv_reg_write_sel is
     when "10000000" => add_lut_src <= Bus2IP_Data(31 downto 24);  -- offset 0x0
     when "01000000" => c_burst_repeat_cnt <= Bus2IP_Data(15 downto 0);  -- offset 0x0
     when "00100000" => c_global_cnt <= Bus2IP_Data(15 downto 0);  -- offset 0x0
     when others => null;
    end case;
   end if;
  end if;
 end process;

 process( slv_reg_read_sel, add_lut_src) is
 begin
  case slv_reg_read_sel is
   when "10000000" => slv_ip2bus_data <= add_lut_src & x"000000";   -- offset 0x0
   when "01000000" => slv_ip2bus_data <= x"00000" & "00" & wr_fifo_full_s & rd_fifo_full_s & sm_status; -- offset 0xc
   when "00100000" => slv_ip2bus_data <= c_burst_repeat_cnt & c_global_cnt;
   when "00010000" => slv_ip2bus_data <= add_cnt & global_cnt;
   when "00001000" => slv_ip2bus_data <= cnt_mst_cmd_sm_set_error & cnt_mst_cmd_sm_set_timeout; -- offset 0xc
   when others => slv_ip2bus_data <= (others => '0');
  end case;
 end process;

 ip2bus_mstrd_dst_dsc_n <= '1'; -- do not throttle data
 ip2bus_mstwr_src_dsc_n <= '1'; -- do not throttle data


 wr_fifo_full <= wr_fifo_full_s;


 start_wr_cmd <= '1' when ((slv_reg_write_sel = "00010000") and (Bus2IP_Data(7 downto 0) = start_wr_cmd_patt)) else '0';
 start_rd_cmd <= '1' when ((slv_reg_write_sel = "00010000") and (Bus2IP_Data(7 downto 0) = start_rd_cmd_patt)) else '0';
 user_rst_cmd <= '1' when ((slv_reg_write_sel = "00010000") and (Bus2IP_Data(7 downto 0) = user_rst_cmd_patt)) else '0';
end IMP;

 

 

system.mhs

 


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.4 Build EDK_O.87xd
# Mon Apr 23 20:31:21 2012
# Target Board:  xilinx.com sp605 Rev C
# Family:    spartan6
# Device:    xc6slx45t
# Package:   fgg484
# Speed Grade:  -3
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT zio = zio, DIR = IO
 PORT rzq = rzq, DIR = IO
 PORT mcbx_dram_we_n = mcbx_dram_we_n, DIR = O
 PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n, DIR = IO
 PORT mcbx_dram_udqs = mcbx_dram_udqs, DIR = IO
 PORT mcbx_dram_udm = mcbx_dram_udm, DIR = O
 PORT mcbx_dram_ras_n = mcbx_dram_ras_n, DIR = O
 PORT mcbx_dram_odt = mcbx_dram_odt, DIR = O
 PORT mcbx_dram_ldm = mcbx_dram_ldm, DIR = O
 PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n, DIR = IO
 PORT mcbx_dram_dqs = mcbx_dram_dqs, DIR = IO
 PORT mcbx_dram_dq = mcbx_dram_dq, DIR = IO, VEC = [15:0]
 PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst, DIR = O
 PORT mcbx_dram_clk_n = mcbx_dram_clk_n, DIR = O, SIGIS = CLK
 PORT mcbx_dram_clk = mcbx_dram_clk, DIR = O, SIGIS = CLK
 PORT mcbx_dram_cke = mcbx_dram_cke, DIR = O
 PORT mcbx_dram_cas_n = mcbx_dram_cas_n, DIR = O
 PORT mcbx_dram_ba = mcbx_dram_ba, DIR = O, VEC = [2:0]
 PORT mcbx_dram_addr = mcbx_dram_addr, DIR = O, VEC = [12:0]
 PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O
 PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I
 PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT LEDs_4Bits_TRI_O = LEDs_4Bits_TRI_O, DIR = O, VEC = [3:0]
 PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
 PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
 PORT wr_fifo_full = axi_user_npi_0_wr_fifo_full, DIR = O
 PORT npi_wr_ready = axi_user_npi_0_npi_wr_ready, DIR = O
 PORT wr_fifo_wr_en = axi_user_npi_0_wr_fifo_wr_en, DIR = I
 PORT wr_fifo_data = axi_user_npi_0_wr_fifo_data, DIR = I, VEC = [31:0]
 PORT npi_rd_ready = axi_user_npi_0_npi_rd_ready, DIR = O
 PORT wr_fifo_clk = axi_user_npi_0_wr_fifo_clk, DIR = I
 PORT rd_fifo_full = axi_user_npi_0_rd_fifo_full, DIR = O
 PORT rd_fifo_clk = axi_user_npi_0_rd_fifo_clk, DIR = I
 PORT rd_fifo_rd_en = axi_user_npi_0_rd_fifo_rd_en, DIR = I
 PORT rd_fifo_data = axi_user_npi_0_rd_fifo_data, DIR = O, VEC = [31:0]
 PORT rd_fifo_empty = axi_user_npi_0_rd_fifo_empty, DIR = O
 PORT wr_fifo_empty = axi_user_npi_0_wr_fifo_empty, DIR = O
 PORT clk_out = clk_50_0000MHzPLL0, DIR = O


BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
 PORT MB_Reset = proc_sys_reset_0_MB_Reset
 PORT Slowest_sync_clk = clk_75_0000MHzPLL0
 PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
 PORT Ext_Reset_In = RESET
 PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_75_0000MHzPLL0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = microblaze_0_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_75_0000MHzPLL0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = microblaze_0_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
 BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 8.20.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0xa0000000
 PARAMETER C_ICACHE_HIGHADDR = 0xbfffffff
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 8192
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_DCACHE_BASEADDR = 0xa0000000
 PARAMETER C_DCACHE_HIGHADDR = 0xbfffffff
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 8192
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 BUS_INTERFACE M_AXI_DP = axi4lite_0
 BUS_INTERFACE M_AXI_IP = axi4lite_0
 BUS_INTERFACE M_AXI_DC = axi4_0
 BUS_INTERFACE M_AXI_IC = axi4_0
 BUS_INTERFACE DEBUG = microblaze_0_debug
 BUS_INTERFACE DLMB = microblaze_0_dlmb
 BUS_INTERFACE ILMB = microblaze_0_ilmb
 PORT MB_RESET = proc_sys_reset_0_MB_Reset
 PORT CLK = clk_75_0000MHzPLL0
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_UART = 1
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
 PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT S_AXI_ACLK = clk_75_0000MHzPLL0
END

BEGIN axi_gpio
 PARAMETER INSTANCE = ddrx_debug
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_GPIO_WIDTH = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_BASEADDR = 0x41000000
 PARAMETER C_HIGHADDR = 0x4100ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_75_0000MHzPLL0
 PORT GPIO_IO_I = uo_done_cal_s
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_CLKIN_FREQ = 200000000
 PARAMETER C_CLKOUT0_FREQ = 600000000
 PARAMETER C_CLKOUT0_GROUP = PLL0
 PARAMETER C_CLKOUT0_BUF = FALSE
 PARAMETER C_CLKOUT1_FREQ = 600000000
 PARAMETER C_CLKOUT1_PHASE = 180
 PARAMETER C_CLKOUT1_GROUP = PLL0
 PARAMETER C_CLKOUT1_BUF = FALSE
 PARAMETER C_CLKOUT2_FREQ = 75000000
 PARAMETER C_CLKOUT2_GROUP = PLL0
 PARAMETER C_CLKOUT3_FREQ = 50000000
 PARAMETER C_CLKOUT3_GROUP = PLL0
 PORT LOCKED = proc_sys_reset_0_Dcm_locked
 PORT CLKOUT2 = clk_75_0000MHzPLL0
 PORT CLKOUT3 = clk_50_0000MHzPLL0
 PORT RST = RESET
 PORT CLKOUT0 = clk_600_0000MHzPLL0_nobuf
 PORT CLKOUT1 = clk_600_0000MHz180PLL0_nobuf
 PORT CLKIN = CLK
END

BEGIN axi_user_npi
 PARAMETER INSTANCE = axi_user_npi_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x60000000
 PARAMETER C_HIGHADDR = 0x6000FFFF
 BUS_INTERFACE M_AXI = axi4_0
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_75_0000MHzPLL0
 PORT m_axi_aclk = clk_75_0000MHzPLL0
 PORT wr_fifo_full = axi_user_npi_0_wr_fifo_full
 PORT npi_wr_ready = axi_user_npi_0_npi_wr_ready
 PORT wr_fifo_wr_en = axi_user_npi_0_wr_fifo_wr_en
 PORT wr_fifo_data = axi_user_npi_0_wr_fifo_data
 PORT npi_rd_ready = axi_user_npi_0_npi_rd_ready
 PORT wr_fifo_clk = axi_user_npi_0_wr_fifo_clk
 PORT rd_fifo_full = axi_user_npi_0_rd_fifo_full
 PORT rd_fifo_clk = axi_user_npi_0_rd_fifo_clk
 PORT rd_fifo_rd_en = axi_user_npi_0_rd_fifo_rd_en
 PORT rd_fifo_data = axi_user_npi_0_rd_fifo_data
 PORT rd_fifo_empty = axi_user_npi_0_rd_fifo_empty
 PORT wr_fifo_empty = axi_user_npi_0_wr_fifo_empty
END

BEGIN bram_block
 PARAMETER INSTANCE = axi_bram_ctrl_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta
 BUS_INTERFACE PORTB = axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb
END

BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = axi_bram_ctrl_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_S_AXI_BASEADDR = 0xB0000000
 PARAMETER C_S_AXI_HIGHADDR = 0xB0003FFF
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta
 BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb
 BUS_INTERFACE S_AXI = axi4_0
 PORT S_AXI_ACLK = clk_75_0000MHzPLL0
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_0
 PARAMETER HW_VER = 1.05.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
 PORT INTERCONNECT_ACLK = clk_75_0000MHzPLL0
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4_0
 PARAMETER HW_VER = 1.05.a
 PORT interconnect_aclk = clk_75_0000MHzPLL0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.99.a
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 1
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_75_0000MHzPLL0
 PORT TX = RS232_Uart_1_sout
 PORT RX = RS232_Uart_1_sin
END

BEGIN axi_s6_ddrx
 PARAMETER INSTANCE = MCB_DDR3
 PARAMETER HW_VER = 1.05.a
 PARAMETER C_MCB_RZQ_LOC = K7
 PARAMETER C_MCB_ZIO_LOC = M7
 PARAMETER C_MEM_TYPE = DDR3
 PARAMETER C_MEM_PARTNO = MT41J64M16XX-187E
 PARAMETER C_MEM_BANKADDR_WIDTH = 3
 PARAMETER C_MEM_NUM_COL_BITS = 10
 PARAMETER C_SKIP_IN_TERM_CAL = 0
 PARAMETER C_S0_AXI_ENABLE = 1
 PARAMETER C_SIMULATION = FALSE
 PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & axi_user_npi_0.M_AXI
 PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 8
 PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 8
 PARAMETER C_INTERCONNECT_S0_AXI_W_REGISTER = 8
 PARAMETER C_INTERCONNECT_S0_AXI_R_REGISTER = 8
 PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 8
 PARAMETER C_S0_AXI_BASEADDR = 0xa8000000
 PARAMETER C_S0_AXI_HIGHADDR = 0xafffffff
 BUS_INTERFACE S0_AXI = axi4_0
 PORT zio = zio
 PORT rzq = rzq
 PORT uo_done_cal = uo_done_cal_s
 PORT s0_axi_aclk = clk_75_0000MHzPLL0
 PORT ui_clk = clk_75_0000MHzPLL0
 PORT mcbx_dram_we_n = mcbx_dram_we_n
 PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n
 PORT mcbx_dram_udqs = mcbx_dram_udqs
 PORT mcbx_dram_udm = mcbx_dram_udm
 PORT mcbx_dram_ras_n = mcbx_dram_ras_n
 PORT mcbx_dram_odt = mcbx_dram_odt
 PORT mcbx_dram_ldm = mcbx_dram_ldm
 PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n
 PORT mcbx_dram_dqs = mcbx_dram_dqs
 PORT mcbx_dram_dq = mcbx_dram_dq
 PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst
 PORT mcbx_dram_clk_n = mcbx_dram_clk_n
 PORT mcbx_dram_clk = mcbx_dram_clk
 PORT mcbx_dram_cke = mcbx_dram_cke
 PORT mcbx_dram_cas_n = mcbx_dram_cas_n
 PORT mcbx_dram_ba = mcbx_dram_ba
 PORT mcbx_dram_addr = mcbx_dram_addr
 PORT sysclk_2x = clk_600_0000MHzPLL0_nobuf
 PORT sysclk_2x_180 = clk_600_0000MHz180PLL0_nobuf
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT PLL_LOCK = proc_sys_reset_0_Dcm_locked
END

BEGIN axi_gpio
 PARAMETER INSTANCE = LEDs_4Bits
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_75_0000MHzPLL0
 PORT GPIO_IO_O = LEDs_4Bits_TRI_O
END

'edk > npi' 카테고리의 다른 글

npi_v4_00_b, latency를 줄인 버전, kc705, ise 14.4  (2) 2013.07.01
axi master design file  (0) 2013.03.12
axi npi  (1) 2012.06.03
axi npi  (0) 2012.04.28
NPI에 대하여  (0) 2011.11.16
NPI를 구성하는 파일들....  (0) 2011.11.16
by Real Xilinx ... xilinx 2012. 4. 28. 12:41
NPI 라는 용어에는 그다지 많은 관심을 가지지 않아도 좋습니다. 

다만 FPGA내부에 있는 메모리는 용량도 적을 뿐만 아니라 다른 여러 목적으로 사용되기 때문에 단순히 데이터를 저장하는 용도로 쓰기에는 적합하지 않습니다.

FPGA 설계자는 FPGA 외부에 메모리를 연결해서 사용하고 싶지만 메모리 콘트롤러를 만드는 것도 만만하지 않습니다.

자일링스는 MPMC라는 메모리 콘트롤러에서 NPI라른 포트를 통해 FPGA 설계자가 FPGA 외부에 있는 메모리를 쉽게 연결해서 사용할 수 있도록 프로토콜을 제공 합니다. 이 프로토콜 이름이 NPI 입니다.

하지만

이것도 어렵습니다는 아니지만이해하고 스테이트 머신을 만들려고 하면 시가이마이 걸립니다.

그래서 NPI_USER_LOGIC_V2_XX_Xuser logic이 외부 메모리를 FIFO 처럼 사용할 수 있도록 해주는 IP 입니다.

아무래도 FIFO를 읽고 쓰는 것은 상대적으로 쉽지 않습니까? 


 

'edk > npi' 카테고리의 다른 글

npi_v4_00_b, latency를 줄인 버전, kc705, ise 14.4  (2) 2013.07.01
axi master design file  (0) 2013.03.12
axi npi  (1) 2012.06.03
axi npi  (0) 2012.04.28
NPI에 대하여  (0) 2011.11.16
NPI를 구성하는 파일들....  (0) 2011.11.16
by Real Xilinx ... xilinx 2011. 11. 16. 17:15


'edk > npi' 카테고리의 다른 글

npi_v4_00_b, latency를 줄인 버전, kc705, ise 14.4  (2) 2013.07.01
axi master design file  (0) 2013.03.12
axi npi  (1) 2012.06.03
axi npi  (0) 2012.04.28
NPI에 대하여  (0) 2011.11.16
NPI를 구성하는 파일들....  (0) 2011.11.16
by Real Xilinx ... xilinx 2011. 11. 16. 17:05
| 1 |