main_exception_daxi.c

 

main_exception_div0.c

 

main.c

 

shell.h

NET LEDs_8Bits_TRI_O[0] LOC = "AC22"  |  IOSTANDARD = "LVCMOS25";
NET LEDs_8Bits_TRI_O[1] LOC = "AC24"  |  IOSTANDARD = "LVCMOS25";
NET LEDs_8Bits_TRI_O[2] LOC = "AE22"  |  IOSTANDARD = "LVCMOS25";
NET LEDs_8Bits_TRI_O[3] LOC = "AE23"  |  IOSTANDARD = "LVCMOS25";
NET LEDs_8Bits_TRI_O[4] LOC = "AB23"  |  IOSTANDARD = "LVCMOS25";
NET LEDs_8Bits_TRI_O[5] LOC = "AG23"  |  IOSTANDARD = "LVCMOS25";
NET LEDs_8Bits_TRI_O[6] LOC = "AE24"  |  IOSTANDARD = "LVCMOS25";
NET LEDs_8Bits_TRI_O[7] LOC = "AD24"  |  IOSTANDARD = "LVCMOS25";

main_float.c

-------------------------------------------------------------------------------
-- system_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity system_top is
  port (
    RS232_Uart_1_sout : out std_logic;
    RS232_Uart_1_sin : in std_logic;
    RESET : in std_logic;
    CLK_P : in std_logic;
    CLK_N : in std_logic;
    ext_int : in std_logic;
    led : inout std_logic_vector(7 downto 0)
  );
end system_top;

architecture STRUCTURE of system_top is

  component system is
    port (
      RS232_Uart_1_sout : out std_logic;
      RS232_Uart_1_sin : in std_logic;
      RESET : in std_logic;
      CLK_P : in std_logic;
      CLK_N : in std_logic;
      ext_int : in std_logic;
      led : inout std_logic_vector(7 downto 0);
      user_add : out std_logic_vector(11 downto 0);
      data_to_user : out std_logic_vector(31 downto 0);
      user_wr : out std_logic;
      data_from_user2 : in std_logic_vector(31 downto 0);
      user_cs : out std_logic_vector(3 downto 0);
      user_rd : out std_logic;
      data_from_user0 : in std_logic_vector(31 downto 0);
      data_from_user1 : in std_logic_vector(31 downto 0);
      data_from_user3 : in std_logic_vector(31 downto 0);
      user_clk : out std_logic
    );
  end component;

  attribute BOX_TYPE : STRING;
  attribute BOX_TYPE of system : component is "user_black_box";

 signal user_clk, user_rd, user_wr : std_logic;
 signal data_to_user, data_from_user0, reg0 : std_logic_vector(31 downto 0);
 signal gnd32 : std_logic_vector(31 downto 0) := x"00000000";
 signal user_cs : std_logic_vector(3 downto 0);
begin

  system_i : system
    port map (
      RS232_Uart_1_sout => RS232_Uart_1_sout,
      RS232_Uart_1_sin => RS232_Uart_1_sin,
      RESET => RESET,
      CLK_P => CLK_P,
      CLK_N => CLK_N,
      ext_int => ext_int,
      led => led,
      user_add => user_add,
      data_to_user => data_to_user,
      user_wr => user_wr,
      user_cs => user_cs,
      user_rd => user_rd,
      data_from_user0 => data_from_user0,
      data_from_user1 => gnd32,
      data_from_user2 => gnd32,
      data_from_user3 => gnd32,
      user_clk => user_clk
    );

 process(user_clk)
 begin
  if user_clk'event and user_clk = '1' then
   if user_cs(0) = '1' then
    if user_rd = '1' then
     case user_add is
      when user_add => x"000"
       data_from_user0 <= reg0;
      when user_add => x"001"
       data_from_user0 <= x"12345678";
      when others => null
     end case;
    end if;

    if user_wr = '1' then
     case user_add is
      when user_add => x"000"
       reg0 <= data_to_user;
      when others => null;
     end case;
    end if;
   end if;
  end if;
 end process;

 

end architecture STRUCTURE;

 

axi_user_logic_32x8192_4cs_v1_00_a.zip

 

main_cache.c

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