Description

For proper L2 cache operation, program the slcr.L2C_RAM register (address 0xF800_0A1C) to the value of 0x0002_0202 before enabling the L2 cache. Programming this register with any other value (including the reset value of 0x0001_0101) can lead to undefined L2 cache behavior



http://www.xilinx.com/support/answers/54190.htm


by Real Xilinx ... xilinx 2013. 2. 19. 09:14
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