KIM HYUK, XILINX EMBEDDED SFAE, Zynq

================= video clip for description ============================ ================= video clip for lab ============================================= video clip source for description ==================== ================= video clip source for lab ============================ ================= vivado ip ============================ ================= shell source code ====================..

---------------------------------------------- video 원본 -------------------------------------------------------------- ---------------------------------------------- 참고파일 -------------------------------------------------------------- ---------------------------------------------- 프로젝트 파일 --------------------------------------------------------------

NPI_V4_10_a를 이용한 메모리 access ========== video clip ===================== ============ video clip ============== projec file ===========

DescriptionFor proper L2 cache operation, program the slcr.L2C_RAM register (address 0xF800_0A1C) to the value of 0x0002_0202 before enabling the L2 cache. Programming this register with any other value (including the reset value of 0x0001_0101) can lead to undefined L2 cache behavior http://www.xilinx.com/support/answers/54190.htm