마이크로블레이즈가 register를 읽고 쓰기 위해 필요한 IP 및 설명

plb_user_logic_32x4096_4cs_10clk_v1_00_a.zip

system.mhs

top.vhd

<< 아래 예는 가장 일반적으로 사용하는 형태 >>

signal reg0, reg1, reg2 : std_logic_vector(0 to 31);

signal user_add : std_logic_vector(0 to 11);

signal user_cs: std_logic_vector(0 to 3);

signal data_from_user0, data_from_user1,data_from_user2, data_from_user3 : std_logic_vector(0 to 31); 

signal data_to_user : std_logic_vector(0 to 31); 

signal user_rd, user_wr, user_clk : std_logic;

begin

Inst_system: system PORT MAP(

ext_int =>ext_int  ,

user_rd =>user_rd  ,

user_clk =>user_clk  ,

user_add => user_add ,

user_wr =>user_wr  ,

data_to_user =>data_to_user  ,

user_cs =>user_cs  ,

data_from_user1 =>data_from_user1  ,

data_from_user2 =>data_from_user2  ,

data_from_user0 =>data_from_user0  ,

data_from_user3 =>data_from_user3  

);

process(user_clk)

begin

if user_clk'event and user_clk = '1' then

if user_cs(0) = '1' then

if user_rd = '1' then

case user_add is

when x"000" => data_from_user0 <= reg0;

when x"001" => data_from_user0 <= reg1;

when x"002" => data_from_user0 <= reg2;

when x"003" => data_from_user0 <= x"12345678"; -- pre define

when others => null;

end case;

end if;

if user_wr = '1' then

case user_add is

when x"000" => reg0 <= data_to_user;

when x"001" => reg1 <= data_to_user;

when x"002" => reg2 <= data_to_user;

when others => null;

end case;

end if;

end if;

end if;

end process;

end Behavioral;

16bits ...
-------------------------------------------------------------------------------
-- system_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity system_top is
 port (
    RS232_Uart_1_sout : out std_logic;
    RS232_Uart_1_sin : in std_logic;
    RESET : in std_logic;
    CLK_P : in std_logic;
    CLK_N : in std_logic
);
end system_top;

architecture STRUCTURE of system_top is

 component system is
  port (
     RS232_Uart_1_sout : out std_logic;
     RS232_Uart_1_sin : in std_logic;
     RESET : in std_logic;
     CLK_P : in std_logic;
     CLK_N : in std_logic;
     user_cs : out std_logic_vector(3 downto 0);
     data_to_user : out std_logic_vector(15 downto 0);
     user_wr : out std_logic;
     data_from_user1 : in std_logic_vector(15 downto 0);
     user_add : out std_logic_vector(11 downto 0);
     data_from_user2 : in std_logic_vector(15 downto 0);
     user_rd : out std_logic;
     data_from_user3 : in std_logic_vector(15 downto 0);
     data_from_user0 : in std_logic_vector(15 downto 0);
     user_clk : out std_logic
    );
 end component;

 attribute BOX_TYPE : STRING;
 attribute BOX_TYPE of system : component is "user_black_box";
 signal reg0, reg1, reg2 : std_logic_vector(15 downto 0);
 signal user_add : std_logic_vector(11 downto 0);
 signal user_cs: std_logic_vector(3 downto 0);
 signal data_from_user0, data_from_user1,data_from_user2, data_from_user3 : std_logic_vector(15 downto 0);
 signal data_to_user : std_logic_vector(15 downto 0);
 signal user_rd, user_wr, user_clk : std_logic;
begin

 system_i : system
 port map (
     RS232_Uart_1_sout => RS232_Uart_1_sout,
     RS232_Uart_1_sin => RS232_Uart_1_sin,
     RESET => RESET,
     CLK_P => CLK_P,
     CLK_N => CLK_N,
     user_cs => user_cs,
     data_to_user => data_to_user,
     user_wr => user_wr,
     data_from_user1 => data_from_user1,
     user_add => user_add,
     data_from_user2 => data_from_user2,
     user_rd => user_rd,
     data_from_user3 => data_from_user3,
     data_from_user0 => data_from_user0,
     user_clk => user_clk
    );

 process(user_clk)
 begin
  if user_clk'event and user_clk = '1' then
   if user_cs(0) = '1' then
    if user_rd = '1' then
     case user_add is
      when x"000" => data_from_user0 <= reg0;
      when x"001" => data_from_user0 <= reg1;
      when x"002" => data_from_user0 <= reg2;
      when x"003" => data_from_user0 <= x"1234"; -- pre define
      when others => null;
     end case;
    end if;

    if user_wr = '1' then
     case user_add is
      when x"000" => reg0 <= data_to_user;
      when x"001" => reg1 <= data_to_user;
      when x"002" => reg2 <= data_to_user;
      when others => null;
     end case;
    end if;
   end if;
  end if;
 end process;
end architecture STRUCTURE;