Design Advisory for Zynq-7000 AP SoC, APU - Proper L2 cache Operation Requires Programming of the slcr.L2C_RAM Register

Description

For proper L2 cache operation, program the slcr.L2C_RAM register (address 0xF800_0A1C) to the value of 0x0002_0202 before enabling the L2 cache. Programming this register with any other value (including the reset value of 0x0001_0101) can lead to undefined L2 cache behavior

http://www.xilinx.com/support/answers/54190.htm