Processor System Reset ModuleReset management moduleDevice SubfamilyNumber of Clocks Before Input Change is Recognized On The External Reset Input Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input External Reset Active High Auxiliary Reset Active High Number of Bus Structure Reset Registered Outputs Number of Peripheral Reset Registered Outputs Number of Active Low Interconnect Reset Registered Outputs Number of Active Low Peripheral Reset Registered Outputs Device FamilyAXI Interrupt Controllerintc core attached to the AXIDevice FamilyC_INSTANCEAXI Base Address AXI High AddressAXI Address WidthAXI Data WidthNumber of Interrupt Inputs Type of Interrupt for Each Input Type of Each Edge Senstive Interrupt Type of Each Level Sensitive Interrupt Support IPR Support SIE Support CIE Support IVR IRQ Output Use Level The Sense of IRQ Output Include Fast Interrupt LogicAXI4LITE protocolEnable Cascade ModeCascade MasterInterrupt InputsInterrupt Request OutputInterrupt Vector Address OutputInterrupt Acknowledgement InputInterrupt_Address_from_downstream_coreInterrupt_Ack_to_downstream_coreLocal Memory Bus (LMB) 1.0'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'Number of Bus Slaves LMB Address Bus Width LMB Data Bus Width Active High External ResetLMB BRAM ControllerLocal Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb busLMB BRAM Base AddressLMB BRAM High AddressSLMB Address Decode MaskSLMB1 Address Decode MaskSLMB2 Address Decode MaskSLMB3 Address Decode MaskLMB Address Bus Width LMB Data Bus Width Error Correction Code Select Interconnect Fault Inject Registers Correctable Error First Failing Register Uncorrectable Error First Failing Register ECC Status and Control Register ECC On/Off Register ECC On/Off Reset Value Correctable Error Counter Register WidthWrite Access setting Number of LMB ports Base Address for PLB InterfaceHigh Address for PLB InterfacePLB Address Bus WidthPLB Data Bus WidthPLB Slave Uses P2P TopologyMaster ID Bus Width of PLBNumber of PLB MastersPLB Slave is Capable of BurstsNative Data Bus Width of PLB SlaveFrequency of PLB SlaveS_AXI_CTRL Clock FrequencyS_AXI_CTRL Base AddressS_AXI_CTRL High AddressS_AXI_CTRL Address WidthS_AXI_CTRL Data WidthS_AXI_CTRL ProtocolLocal Memory Bus (LMB) 1.0'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'Number of Bus Slaves LMB Address Bus Width LMB Data Bus Width Active High External ResetLMB BRAM ControllerLocal Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb busLMB BRAM Base AddressLMB BRAM High AddressSLMB Address Decode MaskSLMB1 Address Decode MaskSLMB2 Address Decode MaskSLMB3 Address Decode MaskLMB Address Bus Width LMB Data Bus Width Error Correction Code Select Interconnect Fault Inject Registers Correctable Error First Failing Register Uncorrectable Error First Failing Register ECC Status and Control Register ECC On/Off Register ECC On/Off Reset Value Correctable Error Counter Register WidthWrite Access setting Number of LMB ports Base Address for PLB InterfaceHigh Address for PLB InterfacePLB Address Bus WidthPLB Data Bus WidthPLB Slave Uses P2P TopologyMaster ID Bus Width of PLBNumber of PLB MastersPLB Slave is Capable of BurstsNative Data Bus Width of PLB SlaveFrequency of PLB SlaveS_AXI_CTRL Clock FrequencyS_AXI_CTRL Base AddressS_AXI_CTRL High AddressS_AXI_CTRL Address WidthS_AXI_CTRL Data WidthS_AXI_CTRL ProtocolBlock RAM (BRAM) BlockThe BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.Size of BRAM(s) in BytesData Width of Port A and BAddress Width of Port A and BNumber of Byte Write EnablesDevice FamilyMicroBlazeThe MicroBlaze 32 bit soft processorEnable Fault Tolerance SupportSelect implementation to optimize area (with lower instruction throughput)Select Bus InterfacesSelect Stream InterfacesEnable Additional Machine Status Register InstructionsEnable Pattern ComparatorEnable Barrel ShifterEnable Integer DividerEnable Integer MultiplierEnable Floating Point UnitEnable Reversed Load/Store and Swap InstructionsEnable Unaligned Data ExceptionEnable Illegal Instruction ExceptionEnable Instruction-side AXI ExceptionEnable Data-side AXI ExceptionEnable Instruction-side PLB ExceptionEnable Data-side PLB ExceptionEnable Integer Divide ExceptionEnable Floating Point Unit ExceptionsEnable Stream Exception<qt>Enable stack protection</qt>Specifies Processor Version RegisterSpecify USER1 Bits in Processor Version RegisterSpecify USER2 Bits in Processor Version RegistersEnable MicroBlaze Debug Module InterfaceNumber of PC Breakpoints Number of Read Address Watchpoints Number of Write Address Watchpoints Sense Interrupt on Edge vs. Level Sense Interrupt on Rising vs. Falling Edge Specify Reset Value for Select MSR Bits<qt>Generate Illegal Instruction Exception for NULL Instruction</qt>Number of Stream Links Enable Additional Stream InstructionsBase Address High Address Enable Instruction Cache Enable WritesSize in BytesLine LengthUse Cache Links for All Memory Accesses Number of VictimsNumber of StreamsUse Distributed RAM for TagsData WidthBase AddressHigh AddressEnable Data CacheEnable WritesSize in BytesLine LengthUse Cache Links for All Memory Accesses Enable Write-back Storage PolicyNumber of VictimsUse Distributed RAM for TagsData WidthMemory ManagementData Shadow Translation Look-Aside Buffer SizeInstruction Shadow Translation Look-Aside Buffer SizeEnable Access to Memory Management Special RegistersNumber of Memory Protection ZonesPrivileged InstructionsEnable Branch Target CacheBranch Target Cache SizeMicroBlaze Debug Module (MDM)Debug module for MicroBlaze Soft Processor.Device FamilySpecifies the JTAG user-defined register used Specifies the Bus Interface for the JTAG UART Base AddressHigh AddressPLB Address Bus WidthPLB Data Bus WidthPLB Slave Uses P2P TopologyMaster ID Bus Width of PLBNumber of PLB MastersNative Data Bus Width of PLB SlavePLB Slave is Capable of BurstsNumber of MicroBlaze debug ports Enable JTAG UART Select BSCAN location AXI Address WidthAXI Data WidthAXI4LITE protocalClock GeneratorClock generator for processor system.FamilyDevicePackageSpeed GradeInput Clock Frequency (Hz) Required Frequency (Hz)Required Phase Required GroupBuffered Variable PhaseRequired Frequency (Hz)Required PhaseRequired Group BufferedVariable PhaseRequired Frequency (Hz)Required PhaseRequired Group BufferedVaraible PhaseRequired Frequency (Hz)Required PhaseRequired GroupBufferedVariable PhaseRequired Frequency (Hz)Required PhaseRequired Group BufferedVariable PhaseRequired Frequency (Hz)Required PhaseRequired GroupBufferedVariable PhaseRequired Frequency (Hz)Required Phase Required GroupBufferedVariable PhaseRequired Frequency (Hz)Required PhaseRequired GroupBufferedVariable PhaseRequired Frequency (Hz)Required PhaseRequired GroupBufferedVariable PhaseRequired Frequency (Hz)Required PhaseRequired GroupBuffered Varaible PhaseRequired Frequency (Hz)Required PhaseRequired GroupBufferedVariable PhaseRequired Frequency (Hz)Required PhaseRequired GroupBufferedVariable PhaseRequired Frequency (Hz)Required PhaseRequired GroupBuffered Variable PhaseRequired Frequency (Hz)Required PhaseRequired GroupBufferedVariable PhaseRequired Frequency (Hz)Required PhaseRequired GroupBufferedVariable PhaseRequired Frequency (Hz)Required PhaseRequired GroupBuffered Variable PhaseRequired Frequency (Hz)Clock DeskewRequired Frequency (Hz)Required PhaseRequired GroupBufferedVariable Phase ShiftC_EXT_RESET_HIGHClock Primitive Feedback BufferAXI InterconnectAXI4 Memory-Mapped InterconnectFamilyBase FamilyNumber of Slave Slots Number of Master Slots AXI ID Widgth AXI Address Widgth AXI Data Maximum Width Slave AXI Data WidthMaster AXI Data Width Interconnect Crossbar Data Width AXI ProtocolMaster AXI ProtocolMaster AXI Base AddressMaster AXI High AddressSlave AXI Base IDSlave AXI Thread ID WidthSlave AXI Is InterconnectSlave AXI ACLK RatioSlvave AXI Is ACLK ASYNCMaster AXI ACLK RatioMaster AXI Is ACLK ASYNCInterconnect Crossbar ACLK Frequency RatioSlave AXI Supports WriteSlave AXI Supports ReadMaster AXI Supports WriteMaster AXI Supports ReadPropagate USER SignalsAWUSER Signal Width ARUSER Signal WidthWUSER Signal Width RUSER Signal WidthBUSER Signal WidthAXI ConnectivitySlave AXI Single ThreadMaster AXI Supports ReorderingMaster generates narrow burstsSlave accepts narrow burstsSlave AXI Write AcceptanceSlave AXI Read AcceptanceMaster AXI Write IssuingMaster AXI Read IssuingSlave AXI ARB PriorityMaster AXI SecureMaster AXI Write FIFO DepthSlave AXI Write FIFO TypeSlave AXI Write FIFO DelaySlave AXI Read FIFO DepthSlave AXI Read FIFO TypeSlave AXI Read FIFO DelayMaster AXI Write FIFO DepthMaster AXI Write FIFO TypeMaster AXI Write FIFO DelayMaster AXI Read FIFO DepthMaster AXI Read FIFO TypeMaster AXI Read FIFO DelaySlave AXI AW RegisterSlave AXI AR RegisterSlave AXI W Register Slave AXI R RegisterSlave AXI B RegisterMaster AXI AW RegisterMaster AXI AR RegisterMaster AXI W RegisterMaster AXI R RegisterMaster AXI B RegisterC_INTERCONNECT_R_REGISTERInterconnect ArchitectureUse Diagnostic Slave PortGenerate InterruptsCheck for transaction errors (DECERR)Slave AXI CTRL ProtocolSlave AXI CTRL Address WidthSlave AXI CTRL Data WidthDiagnostic Slave Port Base AddressDiagnostic Slave Port High AddressSimulation debugSelect SI slot for DEBUG outputsSelect MI slot for DEBUG outputsThread depth of DEBUG signalAXI InterconnectAXI4 Memory-Mapped InterconnectFamilyBase FamilyNumber of Slave Slots Number of Master Slots AXI ID Widgth AXI Address Widgth AXI Data Maximum Width Slave AXI Data WidthMaster AXI Data Width Interconnect Crossbar Data Width AXI ProtocolMaster AXI ProtocolMaster AXI Base AddressMaster AXI High AddressSlave AXI Base IDSlave AXI Thread ID WidthSlave AXI Is InterconnectSlave AXI ACLK RatioSlvave AXI Is ACLK ASYNCMaster AXI ACLK RatioMaster AXI Is ACLK ASYNCInterconnect Crossbar ACLK Frequency RatioSlave AXI Supports WriteSlave AXI Supports ReadMaster AXI Supports WriteMaster AXI Supports ReadPropagate USER SignalsAWUSER Signal Width ARUSER Signal WidthWUSER Signal Width RUSER Signal WidthBUSER Signal WidthAXI ConnectivitySlave AXI Single ThreadMaster AXI Supports ReorderingMaster generates narrow burstsSlave accepts narrow burstsSlave AXI Write AcceptanceSlave AXI Read AcceptanceMaster AXI Write IssuingMaster AXI Read IssuingSlave AXI ARB PriorityMaster AXI SecureMaster AXI Write FIFO DepthSlave AXI Write FIFO TypeSlave AXI Write FIFO DelaySlave AXI Read FIFO DepthSlave AXI Read FIFO TypeSlave AXI Read FIFO DelayMaster AXI Write FIFO DepthMaster AXI Write FIFO TypeMaster AXI Write FIFO DelayMaster AXI Read FIFO DepthMaster AXI Read FIFO TypeMaster AXI Read FIFO DelaySlave AXI AW RegisterSlave AXI AR RegisterSlave AXI W Register Slave AXI R RegisterSlave AXI B RegisterMaster AXI AW RegisterMaster AXI AR RegisterMaster AXI W RegisterMaster AXI R RegisterMaster AXI B RegisterC_INTERCONNECT_R_REGISTERInterconnect ArchitectureUse Diagnostic Slave PortGenerate InterruptsCheck for transaction errors (DECERR)Slave AXI CTRL ProtocolSlave AXI CTRL Address WidthSlave AXI CTRL Data WidthDiagnostic Slave Port Base AddressDiagnostic Slave Port High AddressSimulation debugSelect SI slot for DEBUG outputsSelect MI slot for DEBUG outputsThread depth of DEBUG signalAXI UART (Lite)Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.Device FamilyAXI Clock Frequency AXI Base Address AXI High AddressAXI Address WidthAXI Data WidthUART Lite Baud Rate Baud RateNumber of Data Bits in a Serial FrameData BitsUse Parity Parity Type AXI ProtocolSerial Data OutSerial Data InAXI General Purpose IOGeneral Purpose Input/Output (GPIO) core for the AXI bus.Device FamilyAXI Base Address AXI High AddressAXI Address WidthAXI Data WidthGPIO Data Channel WidthGPIO Data WidthGPIO2 Data Channel WidthChannel 1 is Input Only Channel 2 is Input Only GPIO Supports InterruptsChannel 1 Data Out Default Value Channel 1 3-state Default Value Enable Channel 2 Channel 2 Data Out Default Value Channel 2 3-state Default Value AXI ProtocolGPIO1 Data IOGPIO2 Data IOAXI 7 Series Memory Controller(DDR2/DDR3)7-Series memory controllerAXI_USER_NPIAXI_USER_NPIAXI General Purpose IOGeneral Purpose Input/Output (GPIO) core for the AXI bus.Device FamilyAXI Base Address AXI High AddressAXI Address WidthAXI Data WidthGPIO Data Channel WidthGPIO Data WidthGPIO2 Data Channel WidthChannel 1 is Input Only Channel 2 is Input Only GPIO Supports InterruptsChannel 1 Data Out Default Value Channel 1 3-state Default Value Enable Channel 2 Channel 2 Data Out Default Value Channel 2 3-state Default Value AXI ProtocolGPIO1 Data IOGPIO2 Data IOAXI General Purpose IOGeneral Purpose Input/Output (GPIO) core for the AXI bus.Device FamilyAXI Base Address AXI High AddressAXI Address WidthAXI Data WidthGPIO Data Channel WidthGPIO Data WidthGPIO2 Data Channel WidthChannel 1 is Input Only Channel 2 is Input Only GPIO Supports InterruptsChannel 1 Data Out Default Value Channel 1 3-state Default Value Enable Channel 2 Channel 2 Data Out Default Value Channel 2 3-state Default Value AXI ProtocolGPIO1 Data IOGPIO2 Data IOAXI BRAM ControllerAttaches BRAM to the AXIDevice FamilyAXI4 ProtocolAXI Slave IP Base AddressAXI Slave IP High AddressAXI Slave IP Address WidthAXI Slave IP Data Width or BRAM Data WidthAXI Slave IP ID WidthSlave AXI Supports Narrow BurstsSlave Single Port BRAMInteconnect Slave AXI Read Address Channel RegisterInteconnect Slave AXI Write Address Channel RegisterInteconnect Slave AXI Write Back Channel RegisterInteconnect Slave AXI Read Data Channel RegisterInteconnect Slave AXI Write Data Channel RegisterInteconnect Slave AXI Write AcceptanceInteconnect Slave AXI Read AcceptanceAXI4-Lite ProtocolAXI4-Lite Slave IP Address WidthAXI4-Lite Slave Data WidthAXI4-Lite Slave IP Base AddressAXI4-Lite Slave IP High AddressInteconnect Slave AXI Control Read SupportInteconnect Slave AXI Control Write SupportEnable ECC FunctionalityEnable AXI4-Lite ECC Fault Injection RegistersSet ECC On/Off Reset ValueBlock RAM (BRAM) BlockThe BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.Size of BRAM(s) in BytesData Width of Port A and BAddress Width of Port A and BNumber of Byte Write EnablesDevice Family