# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.3 Build EDK_O.76xd
# Thu Dec 08 15:56:27 2011
# Target Board:  xilinx.com ml605 Rev D
# Family:    virtex6
# Device:    xc6vlx240t
# Package:   ff1156
# Speed Grade:  -1
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT ddr_memory_we_n = ddr_memory_we_n, DIR = O
 PORT ddr_memory_ras_n = ddr_memory_ras_n, DIR = O
 PORT ddr_memory_odt = ddr_memory_odt, DIR = O
 PORT ddr_memory_dqs_n = ddr_memory_dqs_n, DIR = IO, VEC = [0:0]
 PORT ddr_memory_dqs = ddr_memory_dqs, DIR = IO, VEC = [0:0]
 PORT ddr_memory_dq = ddr_memory_dq, DIR = IO, VEC = [7:0]
 PORT ddr_memory_dm = ddr_memory_dm, DIR = O, VEC = [0:0]
 PORT ddr_memory_ddr3_rst = ddr_memory_ddr3_rst, DIR = O
 PORT ddr_memory_cs_n = ddr_memory_cs_n, DIR = O
 PORT ddr_memory_clk_n = ddr_memory_clk_n, DIR = O
 PORT ddr_memory_clk = ddr_memory_clk, DIR = O
 PORT ddr_memory_cke = ddr_memory_cke, DIR = O
 PORT ddr_memory_cas_n = ddr_memory_cas_n, DIR = O
 PORT ddr_memory_ba = ddr_memory_ba, DIR = O, VEC = [2:0]
 PORT ddr_memory_addr = ddr_memory_addr, DIR = O, VEC = [12:0]
 PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O
 PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I
 PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT Linear_Flash_we_n = Linear_Flash_we_n, DIR = O
 PORT Linear_Flash_oe_n = Linear_Flash_oe_n, DIR = O
 PORT Linear_Flash_data = Linear_Flash_data, DIR = IO, VEC = [0:15]
 PORT Linear_Flash_ce_n = Linear_Flash_ce_n, DIR = O
 PORT Linear_Flash_address = Linear_Flash_address, DIR = O, VEC = [0:23]
 PORT IIC_EEPROM_SDA = IIC_EEPROM_SDA, DIR = IO
 PORT IIC_EEPROM_SCL = IIC_EEPROM_SCL, DIR = IO
 PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
 PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
 PORT gpio_i2c_eeprom = gpio_i2c_eeprom_s, DIR = IO, VEC = [1:0]
 PORT gpio_i2c_sfp = gpio_i2c_sfp_s, DIR = IO, VEC = [1:0]


BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
 PORT Slowest_sync_clk = clk_75_0000MHzMMCM0
 PORT MB_Reset = proc_sys_reset_0_MB_Reset
 PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
 PORT Ext_Reset_In = RESET
 PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_150_0000MHzMMCM0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = microblaze_0_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_150_0000MHzMMCM0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = microblaze_0_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
 BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 8.20.a
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0xbc000000
 PARAMETER C_ICACHE_HIGHADDR = 0xbfffffff
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 65536
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_DCACHE_BASEADDR = 0xbc000000
 PARAMETER C_DCACHE_HIGHADDR = 0xbfffffff
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 8192
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 8
 PARAMETER C_INTERCONNECT_M_AXI_DC_AR_REGISTER = 8
 PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 8
 PARAMETER C_INTERCONNECT_M_AXI_DC_R_REGISTER = 8
 PARAMETER C_INTERCONNECT_M_AXI_DC_B_REGISTER = 8
 PARAMETER C_INTERCONNECT_M_AXI_IC_AR_REGISTER = 8
 PARAMETER C_INTERCONNECT_M_AXI_IC_R_REGISTER = 8
 BUS_INTERFACE ILMB = microblaze_0_ilmb
 BUS_INTERFACE DLMB = microblaze_0_dlmb
 BUS_INTERFACE M_AXI_DP = axi4lite_0
 BUS_INTERFACE M_AXI_IP = axi4lite_0
 BUS_INTERFACE M_AXI_DC = axi4_0
 BUS_INTERFACE M_AXI_IC = axi4_0
 BUS_INTERFACE DEBUG = microblaze_0_debug
 PORT MB_RESET = proc_sys_reset_0_MB_Reset
 PORT CLK = clk_150_0000MHzMMCM0
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_UART = 1
 PARAMETER C_BASEADDR = 0x74800000
 PARAMETER C_HIGHADDR = 0x7480ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
 PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT S_AXI_ACLK = clk_75_0000MHzMMCM0
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_CLKIN_FREQ = 200000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_GROUP = MMCM0
 PARAMETER C_CLKOUT1_FREQ = 150000000
 PARAMETER C_CLKOUT1_GROUP = MMCM0
 PARAMETER C_CLKOUT2_FREQ = 200000000
 PARAMETER C_CLKOUT2_GROUP = NONE
 PARAMETER C_CLKOUT3_FREQ = 300000000
 PARAMETER C_CLKOUT3_GROUP = MMCM0
 PARAMETER C_CLKOUT4_FREQ = 300000000
 PARAMETER C_CLKOUT4_GROUP = MMCM0
 PARAMETER C_CLKOUT4_BUF = FALSE
 PARAMETER C_CLKOUT4_VARIABLE_PHASE = TRUE
 PARAMETER C_CLKOUT5_FREQ = 75000000
 PARAMETER C_CLKOUT5_GROUP = MMCM0
 PORT LOCKED = proc_sys_reset_0_Dcm_locked
 PORT CLKOUT0 = clk_100_0000MHzMMCM0
 PORT CLKOUT1 = clk_150_0000MHzMMCM0
 PORT RST = RESET
 PORT CLKOUT5 = clk_75_0000MHzMMCM0
 PORT CLKOUT2 = clk_200_0000MHz
 PORT CLKOUT4 = clk_300_0000MHzMMCM0_nobuf_varphase
 PORT CLKOUT3 = clk_300_0000MHzMMCM0
 PORT CLKIN = CLK
 PORT PSCLK = clk_150_0000MHzMMCM0
 PORT PSEN = psen
 PORT PSINCDEC = psincdec
 PORT PSDONE = psdone
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_0
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
 PORT INTERCONNECT_ACLK = clk_75_0000MHzMMCM0
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4_0
 PARAMETER HW_VER = 1.04.a
 PORT interconnect_aclk = clk_150_0000MHzMMCM0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 1
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT TX = RS232_Uart_1_sout
 PORT RX = RS232_Uart_1_sin
 PORT S_AXI_ACLK = clk_75_0000MHzMMCM0
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = Linear_Flash_invertor
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_OPERATION = not
 PARAMETER C_SIZE = 1
 PORT Op1 = Linear_Flash_invertor_Op1_Adhoc
 PORT Res = Linear_Flash_ce_n
END

BEGIN axi_emc
 PARAMETER INSTANCE = Linear_Flash
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MEM0_WIDTH = 16
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_MEM0_TYPE = 2
 PARAMETER C_TCEDV_PS_MEM_0 = 130000
 PARAMETER C_TAVDV_PS_MEM_0 = 130000
 PARAMETER C_THZCE_PS_MEM_0 = 35000
 PARAMETER C_TWC_PS_MEM_0 = 70000
 PARAMETER C_TWP_PS_MEM_0 = 70000
 PARAMETER C_TLZWE_PS_MEM_0 = 35000
 PARAMETER C_MAX_MEM_WIDTH = 16
 PARAMETER C_S_AXI_MEM0_BASEADDR = 0x76000000
 PARAMETER C_S_AXI_MEM0_HIGHADDR = 0x77ffffff
 BUS_INTERFACE S_AXI_MEM = axi4lite_0
 PORT Mem_WEN = Linear_Flash_we_n
 PORT Mem_OEN = Linear_Flash_oe_n
 PORT Mem_CEN = Linear_Flash_invertor_Op1_Adhoc
 PORT Mem_DQ = Linear_Flash_data
 PORT Mem_A = 0b0000000 & Linear_Flash_address & 0b0
 PORT S_AXI_ACLK = clk_75_0000MHzMMCM0
 PORT RdClk = clk_75_0000MHzMMCM0
END

BEGIN axi_iic
 PARAMETER INSTANCE = IIC_EEPROM
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_IIC_FREQ = 100000
 PARAMETER C_TEN_BIT_ADR = 0
 PARAMETER C_BASEADDR = 0x40800000
 PARAMETER C_HIGHADDR = 0x4080ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_75_0000MHzMMCM0
 PORT Sda = IIC_EEPROM_SDA
 PORT Scl = IIC_EEPROM_SCL
END

BEGIN axi_v6_ddrx
 PARAMETER INSTANCE = DDR3_SDRAM
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_MEM_PARTNO = MT41J64M16XX-15E
 PARAMETER C_DM_WIDTH = 1
 PARAMETER C_DQS_WIDTH = 1
 PARAMETER C_DQ_WIDTH = 8
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC
 PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y8
 PARAMETER C_NDQS_COL0 = 1
 PARAMETER C_NDQS_COL1 = 0
 PARAMETER C_S_AXI_BASEADDR = 0xbc000000
 PARAMETER C_S_AXI_HIGHADDR = 0xbfffffff
 BUS_INTERFACE S_AXI = axi4_0
 PORT clk = clk_150_0000MHzMMCM0
 PORT ddr_we_n = ddr_memory_we_n
 PORT ddr_ras_n = ddr_memory_ras_n
 PORT ddr_odt = ddr_memory_odt
 PORT ddr_dqs_n = ddr_memory_dqs_n
 PORT ddr_dqs_p = ddr_memory_dqs
 PORT ddr_dq = ddr_memory_dq
 PORT ddr_dm = ddr_memory_dm
 PORT ddr_reset_n = ddr_memory_ddr3_rst
 PORT ddr_cs_n = ddr_memory_cs_n
 PORT ddr_ck_n = ddr_memory_clk_n
 PORT ddr_ck_p = ddr_memory_clk
 PORT ddr_cke = ddr_memory_cke
 PORT ddr_cas_n = ddr_memory_cas_n
 PORT ddr_ba = ddr_memory_ba
 PORT ddr_addr = ddr_memory_addr
 PORT clk_ref = clk_200_0000MHz
 PORT clk_rd_base = clk_300_0000MHzMMCM0_nobuf_varphase
 PORT clk_mem = clk_300_0000MHzMMCM0
 PORT PD_PSEN = psen
 PORT PD_PSINCDEC = psincdec
 PORT PD_PSDONE = psdone
END

BEGIN axi_gpio
 PARAMETER INSTANCE = axi_gpio_i2c_eeprom
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_GPIO_WIDTH = 2
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_75_0000MHzMMCM0
 PORT GPIO_IO = gpio_i2c_eeprom_s
END

BEGIN axi_gpio
 PARAMETER INSTANCE = axi_gpio_i2c_sfp
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_GPIO_WIDTH = 2
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_75_0000MHzMMCM0
 PORT GPIO_IO = gpio_i2c_sfp_s
END

BEGIN axi_timer
 PARAMETER INSTANCE = axi_timer_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_BASEADDR = 0x41c00000
 PARAMETER C_HIGHADDR = 0x41c0ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_75_0000MHzMMCM0
END