# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.4 Build EDK_O.87xd
# Thu Feb 09 00:14:47 2012
# Target Board:  xilinx.com ml605 Rev D
# Family:    virtex6
# Device:    xc6vlx240t
# Package:   ff1156
# Speed Grade:  -1
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT ddr_memory_we_n = ddr_memory_we_n, DIR = O
 PORT ddr_memory_ras_n = ddr_memory_ras_n, DIR = O
 PORT ddr_memory_odt = ddr_memory_odt, DIR = O
 PORT ddr_memory_dqs_n = ddr_memory_dqs_n, DIR = IO, VEC = [0:0]
 PORT ddr_memory_dqs = ddr_memory_dqs, DIR = IO, VEC = [0:0]
 PORT ddr_memory_dq = ddr_memory_dq, DIR = IO, VEC = [7:0]
 PORT ddr_memory_dm = ddr_memory_dm, DIR = O, VEC = [0:0]
 PORT ddr_memory_ddr3_rst = ddr_memory_ddr3_rst, DIR = O
 PORT ddr_memory_cs_n = ddr_memory_cs_n, DIR = O
 PORT ddr_memory_clk_n = ddr_memory_clk_n, DIR = O
 PORT ddr_memory_clk = ddr_memory_clk, DIR = O
 PORT ddr_memory_cke = ddr_memory_cke, DIR = O
 PORT ddr_memory_cas_n = ddr_memory_cas_n, DIR = O
 PORT ddr_memory_ba = ddr_memory_ba, DIR = O, VEC = [2:0]
 PORT ddr_memory_addr = ddr_memory_addr, DIR = O, VEC = [12:0]
 PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O
 PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I
 PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT Linear_Flash_we_n = Linear_Flash_we_n, DIR = O
 PORT Linear_Flash_oe_n = Linear_Flash_oe_n, DIR = O
 PORT Linear_Flash_data = Linear_Flash_data, DIR = IO, VEC = [0:15]
# PORT Linear_Flash_ce_n = Linear_Flash_ce_n, DIR = O
 PORT Linear_Flash_address = Linear_Flash_address, DIR = O, VEC = [0:23]
 PORT fpga_0_FLASH_CE_inverter_Res_pin = net_gnd, DIR = O
 PORT fpga_0_PLATFLASH_L_B_pin = net_gnd, DIR = O
 PORT FPGA_FCS_B = net_bsbassign0, DIR = O
 PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
 PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
 PORT bram_clk_0 = axi_user_bram_ctrl_4kbyte_0_bram_clk, DIR = O
 PORT bram_add_0 = axi_user_bram_ctrl_4kbyte_0_bram_add, DIR = O, VEC = [9:0]
 PORT bram_cs_0 = axi_user_bram_ctrl_4kbyte_0_bram_cs, DIR = O
 PORT bram_din_0 = axi_user_bram_ctrl_4kbyte_0_bram_din, DIR = O, VEC = [31:0]
 PORT bram_we_0 = axi_user_bram_ctrl_4kbyte_0_bram_we, DIR = O, VEC = [3:0]
 PORT bram_dout_0 = axi_user_bram_ctrl_4kbyte_0_bram_dout, DIR = I, VEC = [31:0]
 PORT bram_clk_1 = axi_user_bram_ctrl_4kbyte_1_bram_clk, DIR = O
 PORT bram_we_1 = axi_user_bram_ctrl_4kbyte_1_bram_we, DIR = O, VEC = [3:0]
 PORT bram_dout_1 = axi_user_bram_ctrl_4kbyte_1_bram_dout, DIR = I, VEC = [31:0]
 PORT bram_add_1 = axi_user_bram_ctrl_4kbyte_1_bram_add, DIR = O, VEC = [9:0]
 PORT bram_din_1 = axi_user_bram_ctrl_4kbyte_1_bram_din, DIR = O, VEC = [31:0]
 PORT bram_cs_1 = axi_user_bram_ctrl_4kbyte_1_bram_cs, DIR = O


BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
 PORT MB_Reset = proc_sys_reset_0_MB_Reset
 PORT Slowest_sync_clk = clk_100_0000MHzMMCM0
 PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
 PORT Ext_Reset_In = RESET
 PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_1_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHzMMCM0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_1_i_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = microblaze_1_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_1_i_bram_ctrl_2_microblaze_1_bram_block
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_1_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHzMMCM0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_1_d_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = microblaze_1_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_1_d_bram_ctrl_2_microblaze_1_bram_block
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_1_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = microblaze_1_i_bram_ctrl_2_microblaze_1_bram_block
 BUS_INTERFACE PORTB = microblaze_1_d_bram_ctrl_2_microblaze_1_bram_block
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_1
 PARAMETER HW_VER = 8.20.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0xa4000000
 PARAMETER C_ICACHE_HIGHADDR = 0xa7ffffff
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 8192
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_DCACHE_BASEADDR = 0xa4000000
 PARAMETER C_DCACHE_HIGHADDR = 0xa7ffffff
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 8192
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 BUS_INTERFACE ILMB = microblaze_1_ilmb
 BUS_INTERFACE DLMB = microblaze_1_dlmb
 BUS_INTERFACE M_AXI_DP = axi4lite_1
 BUS_INTERFACE M_AXI_DC = axi4_0
 BUS_INTERFACE M_AXI_IC = axi4_0
 BUS_INTERFACE DEBUG = microblaze_1_debug
 PORT MB_RESET = proc_sys_reset_0_MB_Reset
 PORT CLK = clk_100_0000MHzMMCM0
END

BEGIN axi_intc
 PARAMETER INSTANCE = microblaze_0_intc
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT IRQ = microblaze_0_interrupt
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT INTR = axi_timer_0_Interrupt
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHzMMCM0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = microblaze_0_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHzMMCM0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = microblaze_0_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
 BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 8.20.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0xa4000000
 PARAMETER C_ICACHE_HIGHADDR = 0xa7ffffff
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 8192
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_DCACHE_BASEADDR = 0xa4000000
 PARAMETER C_DCACHE_HIGHADDR = 0xa7ffffff
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 8192
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 BUS_INTERFACE ILMB = microblaze_0_ilmb
 BUS_INTERFACE DLMB = microblaze_0_dlmb
 BUS_INTERFACE M_AXI_DP = axi4lite_0
 BUS_INTERFACE M_AXI_DC = axi4_0
 BUS_INTERFACE M_AXI_IC = axi4_0
 BUS_INTERFACE DEBUG = microblaze_0_debug
 PORT MB_RESET = proc_sys_reset_0_MB_Reset
 PORT CLK = clk_100_0000MHzMMCM0
 PORT INTERRUPT = microblaze_0_interrupt
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_UART = 1
 PARAMETER C_MB_DBG_PORTS = 2
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE S_AXI = axi4lite_1
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
 BUS_INTERFACE MBDEBUG_1 = microblaze_1_debug
 PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_CLKIN_FREQ = 200000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_GROUP = MMCM0
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_GROUP = MMCM0
 PARAMETER C_CLKOUT2_FREQ = 400000000
 PARAMETER C_CLKOUT2_GROUP = MMCM0
 PARAMETER C_CLKOUT3_FREQ = 400000000
 PARAMETER C_CLKOUT3_GROUP = MMCM0
 PARAMETER C_CLKOUT3_BUF = FALSE
 PARAMETER C_CLKOUT3_VARIABLE_PHASE = TRUE
 PORT LOCKED = proc_sys_reset_0_Dcm_locked
 PORT CLKOUT0 = clk_100_0000MHzMMCM0
 PORT RST = RESET
 PORT CLKOUT3 = clk_400_0000MHzMMCM0_nobuf_varphase
 PORT CLKOUT2 = clk_400_0000MHzMMCM0
 PORT CLKOUT1 = clk_200_0000MHzMMCM0
 PORT CLKIN = CLK
 PORT PSCLK = clk_200_0000MHzMMCM0
 PORT PSEN = psen
 PORT PSINCDEC = psincdec
 PORT PSDONE = psdone
END

BEGIN axi_user_bram_ctrl_4kbyte
 PARAMETER INSTANCE = axi_user_bram_ctrl_4kbyte_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_S_AXI_MEM0_BASEADDR = 0x10000000
 PARAMETER C_S_AXI_MEM0_HIGHADDR = 0x10000FFF
 BUS_INTERFACE S_AXI = axi4lite_1
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT bram_clk = axi_user_bram_ctrl_4kbyte_1_bram_clk
 PORT bram_we = axi_user_bram_ctrl_4kbyte_1_bram_we
 PORT bram_dout = axi_user_bram_ctrl_4kbyte_1_bram_dout
 PORT bram_add = axi_user_bram_ctrl_4kbyte_1_bram_add
 PORT bram_din = axi_user_bram_ctrl_4kbyte_1_bram_din
 PORT bram_cs = axi_user_bram_ctrl_4kbyte_1_bram_cs
END

BEGIN axi_user_bram_ctrl_4kbyte
 PARAMETER INSTANCE = axi_user_bram_ctrl_4kbyte_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_S_AXI_MEM0_BASEADDR = 0x10000000
 PARAMETER C_S_AXI_MEM0_HIGHADDR = 0x10000FFF
 PARAMETER C_S_AXI_ID_WIDTH = 2
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT bram_clk = axi_user_bram_ctrl_4kbyte_0_bram_clk
 PORT bram_add = axi_user_bram_ctrl_4kbyte_0_bram_add
 PORT bram_cs = axi_user_bram_ctrl_4kbyte_0_bram_cs
 PORT bram_din = axi_user_bram_ctrl_4kbyte_0_bram_din
 PORT bram_we = axi_user_bram_ctrl_4kbyte_0_bram_we
 PORT bram_dout = axi_user_bram_ctrl_4kbyte_0_bram_dout
END

BEGIN axi_timer
 PARAMETER INSTANCE = axi_timer_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER C_BASEADDR = 0x41c00000
 PARAMETER C_HIGHADDR = 0x41c0ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT Interrupt = axi_timer_0_Interrupt
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_0
 PARAMETER HW_VER = 1.05.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
 PORT INTERCONNECT_ACLK = clk_100_0000MHzMMCM0
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4_0
 PARAMETER HW_VER = 1.05.a
 PORT interconnect_aclk = clk_100_0000MHzMMCM0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 1
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT TX = RS232_Uart_1_sout
 PORT RX = RS232_Uart_1_sin
END

# BEGIN util_vector_logic
# PARAMETER INSTANCE = Linear_Flash_invertor
# PARAMETER HW_VER = 1.00.a
# PARAMETER C_OPERATION = not
# PARAMETER C_SIZE = 1
# PORT Op1 = Linear_Flash_invertor_Op1_Adhoc
# PORT Res = Linear_Flash_ce_n
# END
BEGIN axi_emc
 PARAMETER INSTANCE = Linear_Flash
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MEM0_WIDTH = 16
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_MEM0_TYPE = 2
 PARAMETER C_TCEDV_PS_MEM_0 = 130000
 PARAMETER C_TAVDV_PS_MEM_0 = 130000
 PARAMETER C_THZCE_PS_MEM_0 = 35000
 PARAMETER C_TWC_PS_MEM_0 = 70000
 PARAMETER C_TWP_PS_MEM_0 = 70000
 PARAMETER C_TLZWE_PS_MEM_0 = 35000
 PARAMETER C_MAX_MEM_WIDTH = 16
 PARAMETER C_S_AXI_MEM0_BASEADDR = 0x46000000
 PARAMETER C_S_AXI_MEM0_HIGHADDR = 0x47ffffff
 BUS_INTERFACE S_AXI_MEM = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT RdClk = clk_100_0000MHzMMCM0
 PORT Mem_WEN = Linear_Flash_we_n
 PORT Mem_OEN = Linear_Flash_oe_n
# PORT Mem_CEN = Linear_Flash_invertor_Op1_Adhoc
 PORT Mem_CEN = net_bsbassign0
 PORT Mem_DQ = Linear_Flash_data
 PORT Mem_A = 0b0000000 & Linear_Flash_address & 0b0
END

BEGIN axi_v6_ddrx
 PARAMETER INSTANCE = DDR3_SDRAM
 PARAMETER HW_VER = 1.05.a
 PARAMETER C_MEM_PARTNO = MT41J64M16XX-15E
 PARAMETER C_DM_WIDTH = 1
 PARAMETER C_DQS_WIDTH = 1
 PARAMETER C_DQ_WIDTH = 8
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & microblaze_1.M_AXI_DC & microblaze_1.M_AXI_IC
 PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y8
 PARAMETER C_NDQS_COL0 = 1
 PARAMETER C_NDQS_COL1 = 0
 PARAMETER C_S_AXI_BASEADDR = 0xa4000000
 PARAMETER C_S_AXI_HIGHADDR = 0xa7ffffff
 BUS_INTERFACE S_AXI = axi4_0
 PORT ddr_we_n = ddr_memory_we_n
 PORT ddr_ras_n = ddr_memory_ras_n
 PORT ddr_odt = ddr_memory_odt
 PORT ddr_dqs_n = ddr_memory_dqs_n
 PORT ddr_dqs_p = ddr_memory_dqs
 PORT ddr_dq = ddr_memory_dq
 PORT ddr_dm = ddr_memory_dm
 PORT ddr_reset_n = ddr_memory_ddr3_rst
 PORT ddr_cs_n = ddr_memory_cs_n
 PORT ddr_ck_n = ddr_memory_clk_n
 PORT ddr_ck_p = ddr_memory_clk
 PORT ddr_cke = ddr_memory_cke
 PORT ddr_cas_n = ddr_memory_cas_n
 PORT ddr_ba = ddr_memory_ba
 PORT ddr_addr = ddr_memory_addr
 PORT clk_rd_base = clk_400_0000MHzMMCM0_nobuf_varphase
 PORT clk_mem = clk_400_0000MHzMMCM0
 PORT clk = clk_200_0000MHzMMCM0
 PORT clk_ref = clk_200_0000MHzMMCM0
 PORT PD_PSEN = psen
 PORT PD_PSINCDEC = psincdec
 PORT PD_PSDONE = psdone
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_1
 PARAMETER HW_VER = 1.05.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
 PORT INTERCONNECT_ACLK = clk_100_0000MHzMMCM0
END