# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 12.3 Build EDK_MS3.70d
# Tue Mar 29 22:45:50 2011
# Target Board:  Xilinx Virtex 6 ML605 Evaluation Platform Rev D
# Family:    virtex6
# Device:    xc6vlx240t
# Package:   ff1156
# Speed Grade:  -1
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 100.0
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
 PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
 PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30]
 PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN_pin, DIR = O
 PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN_pin, DIR = O
 PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ_pin, DIR = IO, VEC = [0:15]
 PORT fpga_0_DDR3_SDRAM_DDR3_Clk_pin = fpga_0_DDR3_SDRAM_DDR3_Clk_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin = fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_CE_pin = fpga_0_DDR3_SDRAM_DDR3_CE_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_CS_n_pin = fpga_0_DDR3_SDRAM_DDR3_CS_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_ODT_pin = fpga_0_DDR3_SDRAM_DDR3_ODT_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin = fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin = fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_WE_n_pin = fpga_0_DDR3_SDRAM_DDR3_WE_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin = fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin, DIR = O, VEC = [2:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_Addr_pin = fpga_0_DDR3_SDRAM_DDR3_Addr_pin, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_DQ_pin = fpga_0_DDR3_SDRAM_DDR3_DQ_pin, DIR = IO, VEC = [31:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_DM_pin = fpga_0_DDR3_SDRAM_DDR3_DM_pin, DIR = O, VEC = [3:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin = fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_DQS_pin = fpga_0_DDR3_SDRAM_DDR3_DQS_pin, DIR = IO, VEC = [3:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin = fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin, DIR = IO, VEC = [3:0]
 PORT fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin, DIR = O, VEC = [7:0]
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin, DIR = I, VEC = [7:0]
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_MDC_0_pin = fpga_0_Hard_Ethernet_MAC_MDC_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_MDIO_0_pin = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin, DIR = IO
 PORT fpga_0_clk_1_sys_clk_p_pin = dcm_clk_s, DIR = I, SIGIS = CLK, DIFFERENTIAL_POLARITY = P, CLK_FREQ = 200000000
 PORT fpga_0_clk_1_sys_clk_n_pin = dcm_clk_s, DIR = I, SIGIS = CLK, DIFFERENTIAL_POLARITY = N, CLK_FREQ = 200000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT fpga_0_FLASH_CE_inverter_Res_pin = fpga_0_FLASH_CE_inverter_Res_pin, DIR = O
 PORT ext_int = ext_int_s, DIR = I, SIGIS = INTERRUPT
 PORT user_rd = plb_user_logic_32x4096_4cs_10clk_0_user_rd, DIR = O
 PORT user_clk = plb_user_logic_32x4096_4cs_10clk_0_user_clk, DIR = O
 PORT user_add = plb_user_logic_32x4096_4cs_10clk_0_user_add, DIR = O, VEC = [0:11]
 PORT user_wr = plb_user_logic_32x4096_4cs_10clk_0_user_wr, DIR = O
 PORT data_to_user = plb_user_logic_32x4096_4cs_10clk_0_data_to_user, DIR = O, VEC = [0:31]
 PORT user_cs = plb_user_logic_32x4096_4cs_10clk_0_user_cs, DIR = O, VEC = [0:3]
 PORT data_from_user1 = plb_user_logic_32x4096_4cs_10clk_0_data_from_user1, DIR = I, VEC = [0:31]
 PORT data_from_user2 = plb_user_logic_32x4096_4cs_10clk_0_data_from_user2, DIR = I, VEC = [0:31]
 PORT data_from_user0 = plb_user_logic_32x4096_4cs_10clk_0_data_from_user0, DIR = I, VEC = [0:31]
 PORT data_from_user3 = plb_user_logic_32x4096_4cs_10clk_0_data_from_user3, DIR = I, VEC = [0:31]


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_FPU = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0x50000000
 PARAMETER C_ICACHE_HIGHADDR = 0x5fffffff
 PARAMETER C_CACHE_BYTE_SIZE = 2048
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_DCACHE_BASEADDR = 0x50000000
 PARAMETER C_DCACHE_HIGHADDR = 0x5fffffff
 PARAMETER C_DCACHE_BYTE_SIZE = 2048
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 PARAMETER HW_VER = 8.00.a
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_USE_DIV = 1
 PARAMETER C_FPU_EXCEPTION = 1
 PARAMETER C_DIV_ZERO_EXCEPTION = 1
 PARAMETER C_DPLB_BUS_EXCEPTION = 1
 PARAMETER C_IPLB_BUS_EXCEPTION = 1
 PARAMETER C_ILL_OPCODE_EXCEPTION = 1
 PARAMETER C_UNALIGNED_EXCEPTIONS = 1
 PARAMETER C_PVR = 1
 PARAMETER C_PVR_USER2 = 0x20110300
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DXCL = microblaze_0_DXCL
 BUS_INTERFACE IXCL = microblaze_0_IXCL
 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 PORT MB_RESET = mb_reset
 PORT INTERRUPT = microblaze_0_Interrupt
 PORT Trace_Instruction = Trace_Instruction
 PORT Trace_Valid_Instr = Trace_Valid_Instr
 PORT Trace_PC = Trace_PC
 PORT FSL0_M_CLK = microblaze_0_FSL0_M_CLK_to_chipscope_ila_0
 PORT FSL0_M_CONTROL = microblaze_0_FSL0_M_CONTROL_to_chipscope_ila_0
 PORT FSL0_M_DATA = microblaze_0_FSL0_M_DATA_to_chipscope_ila_0
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.05.a
 PORT PLB_Clk = clk_100_0000MHzMMCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_100_0000MHzMMCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_100_0000MHzMMCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_Uart_1_RX_pin
 PORT TX = fpga_0_RS232_Uart_1_TX_pin
 PORT Interrupt = RS232_Uart_1_Interrupt
END

BEGIN xps_gpio
 PARAMETER INSTANCE = LEDs_8Bit
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81400000
 PARAMETER C_HIGHADDR = 0x8140ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO_pin
END

BEGIN xps_mch_emc
 PARAMETER INSTANCE = FLASH
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_NUM_CHANNELS = 0
 PARAMETER C_MEM0_WIDTH = 16
 PARAMETER C_MAX_MEM_WIDTH = 16
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_SYNCH_MEM_0 = 0
 PARAMETER C_TCEDV_PS_MEM_0 = 110000
 PARAMETER C_TAVDV_PS_MEM_0 = 110000
 PARAMETER C_THZCE_PS_MEM_0 = 35000
 PARAMETER C_TWC_PS_MEM_0 = 11000
 PARAMETER C_TWP_PS_MEM_0 = 70000
 PARAMETER C_TLZWE_PS_MEM_0 = 35000
 PARAMETER HW_VER = 3.01.a
 PARAMETER C_MEM0_BASEADDR = 0x86000000
 PARAMETER C_MEM0_HIGHADDR = 0x87ffffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RdClk = clk_100_0000MHzMMCM0
 PORT Mem_A = 0b0000000 & fpga_0_FLASH_Mem_A_pin_vslice_7_30_concat & 0b0
 PORT Mem_CEN = net_bsbassign0
 PORT Mem_OEN = fpga_0_FLASH_Mem_OEN_pin
 PORT Mem_WEN = fpga_0_FLASH_Mem_WEN_pin
 PORT Mem_DQ = fpga_0_FLASH_Mem_DQ_pin
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR3_SDRAM
 PARAMETER C_NUM_PORTS = 3
 PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y9
 PARAMETER C_MEM_TYPE = DDR3
 PARAMETER C_MEM_PARTNO = MT4JSF6464HY-1G1
 PARAMETER C_MEM_ODT_TYPE = 1
 PARAMETER C_MEM_REG_DIMM = 0
 PARAMETER C_MEM_CLK_WIDTH = 1
 PARAMETER C_MEM_ODT_WIDTH = 1
 PARAMETER C_MEM_CE_WIDTH = 1
 PARAMETER C_MEM_CS_N_WIDTH = 1
 PARAMETER C_MEM_DATA_WIDTH = 32
 PARAMETER C_MEM_NDQS_COL0 = 3
 PARAMETER C_MEM_NDQS_COL1 = 1
 PARAMETER C_MEM_DQS_LOC_COL0 = 0x000000000000000000000000000000020100
 PARAMETER C_MEM_DQS_LOC_COL1 = 0x000000000000000000000000000000000003
 PARAMETER C_PIM0_BASETYPE = 1
 PARAMETER C_PIM1_BASETYPE = 1
 PARAMETER C_PIM2_BASETYPE = 3
 PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 2
 PARAMETER HW_VER = 6.02.a
 PARAMETER C_MPMC_BASEADDR = 0x50000000
 PARAMETER C_MPMC_HIGHADDR = 0x5fffffff
 PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000
 PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460ffff
 BUS_INTERFACE XCL0 = microblaze_0_IXCL
 BUS_INTERFACE XCL1 = microblaze_0_DXCL
 BUS_INTERFACE SDMA_CTRL2 = mb_plb
 BUS_INTERFACE SDMA_LL2 = Hard_Ethernet_MAC_LLINK0
 PORT SDMA2_Clk = clk_100_0000MHzMMCM0
 PORT SDMA2_Rx_IntOut = DDR3_SDRAM_SDMA2_Rx_IntOut
 PORT SDMA2_Tx_IntOut = DDR3_SDRAM_SDMA2_Tx_IntOut
 PORT MPMC_Clk0 = clk_200_0000MHzMMCM0
 PORT MPMC_Clk_200MHz = clk_200_0000MHzMMCM0
 PORT MPMC_Rst = sys_periph_reset
 PORT MPMC_Clk_Mem = clk_400_0000MHzMMCM0
 PORT MPMC_Clk_Rd_Base = clk_400_0000MHzMMCM0_nobuf_varphase
 PORT MPMC_DCM_PSEN = MPMC_DCM_PSEN
 PORT MPMC_DCM_PSINCDEC = MPMC_DCM_PSINCDEC
 PORT MPMC_DCM_PSDONE = MPMC_DCM_PSDONE
 PORT DDR3_Clk = fpga_0_DDR3_SDRAM_DDR3_Clk_pin
 PORT DDR3_Clk_n = fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin
 PORT DDR3_CE = fpga_0_DDR3_SDRAM_DDR3_CE_pin
 PORT DDR3_CS_n = fpga_0_DDR3_SDRAM_DDR3_CS_n_pin
 PORT DDR3_ODT = fpga_0_DDR3_SDRAM_DDR3_ODT_pin
 PORT DDR3_RAS_n = fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin
 PORT DDR3_CAS_n = fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin
 PORT DDR3_WE_n = fpga_0_DDR3_SDRAM_DDR3_WE_n_pin
 PORT DDR3_BankAddr = fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin
 PORT DDR3_Addr = fpga_0_DDR3_SDRAM_DDR3_Addr_pin
 PORT DDR3_DQ = fpga_0_DDR3_SDRAM_DDR3_DQ_pin
 PORT DDR3_DM = fpga_0_DDR3_SDRAM_DDR3_DM_pin
 PORT DDR3_Reset_n = fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin
 PORT DDR3_DQS = fpga_0_DDR3_SDRAM_DDR3_DQS_pin
 PORT DDR3_DQS_n = fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin
END

BEGIN xps_ll_temac
 PARAMETER INSTANCE = Hard_Ethernet_MAC
 PARAMETER C_NUM_IDELAYCTRL = 1
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X2Y1
 PARAMETER C_PHY_TYPE = 1
 PARAMETER C_TEMAC1_ENABLED = 0
 PARAMETER C_BUS2CORE_CLK_RATIO = 1
 PARAMETER C_TEMAC_TYPE = 3
 PARAMETER C_TEMAC0_PHYADDR = 0b00001
 PARAMETER HW_VER = 2.03.a
 PARAMETER C_BASEADDR = 0x85380000
 PARAMETER C_HIGHADDR = 0x853fffff
 PARAMETER C_TEMAC0_TXCSUM = 1
 PARAMETER C_TEMAC0_RXCSUM = 1
 PARAMETER C_TEMAC0_STATS = 1
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE LLINK0 = Hard_Ethernet_MAC_LLINK0
 PORT TemacIntc0_Irpt = Hard_Ethernet_MAC_TemacIntc0_Irpt
 PORT TemacPhy_RST_n = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin
 PORT GTX_CLK_0 = clk_125_0000MHz
 PORT REFCLK = clk_200_0000MHzMMCM0
 PORT LlinkTemac0_CLK = clk_100_0000MHzMMCM0
 PORT MII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin
 PORT GMII_TXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin
 PORT GMII_TX_EN_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin
 PORT GMII_TX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin
 PORT GMII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin
 PORT GMII_RXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin
 PORT GMII_RX_DV_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin
 PORT GMII_RX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin
 PORT GMII_RX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin
 PORT MDC_0 = fpga_0_Hard_Ethernet_MAC_MDC_0_pin
 PORT MDIO_0 = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_0
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x83c20000
 PARAMETER C_HIGHADDR = 0x83c2ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Interrupt = xps_timer_0_Interrupt
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_1
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x83c00000
 PARAMETER C_HIGHADDR = 0x83c0ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Interrupt = xps_timer_1_Interrupt
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = FLASH_CE_inverter
 PARAMETER C_OPERATION = not
 PARAMETER C_SIZE = 1
 PARAMETER HW_VER = 1.00.a
 PORT Op1 = net_bsbassign0
 PORT Res = fpga_0_FLASH_CE_inverter_Res_pin
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 200000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = MMCM0
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 125000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = NONE
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 200000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = MMCM0
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT3_FREQ = 400000000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = MMCM0
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_CLKOUT4_FREQ = 400000000
 PARAMETER C_CLKOUT4_PHASE = 0
 PARAMETER C_CLKOUT4_GROUP = MMCM0
 PARAMETER C_CLKOUT4_BUF = FALSE
 PARAMETER C_CLKOUT4_VARIABLE_PHASE = TRUE
 PARAMETER C_PSDONE_GROUP = MMCM0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 4.00.a
 PORT CLKIN = dcm_clk_s
 PORT CLKOUT0 = clk_100_0000MHzMMCM0
 PORT CLKOUT1 = clk_125_0000MHz
 PORT CLKOUT2 = clk_200_0000MHzMMCM0
 PORT CLKOUT3 = clk_400_0000MHzMMCM0
 PORT CLKOUT4 = clk_400_0000MHzMMCM0_nobuf_varphase
 PORT PSCLK = clk_200_0000MHzMMCM0
 PORT PSEN = MPMC_DCM_PSEN
 PORT PSINCDEC = MPMC_DCM_PSINCDEC
 PORT PSDONE = MPMC_DCM_PSDONE
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
END

BEGIN mdm
 PARAMETER INSTANCE = mdm_0
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 3.00.a
 PORT Slowest_sync_clk = clk_100_0000MHzMMCM0
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Dcm_locked = Dcm_all_locked
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Intr = RS232_Uart_1_Interrupt & ext_int_s & Hard_Ethernet_MAC_TemacIntc0_Irpt & xps_timer_1_Interrupt & DDR3_SDRAM_SDMA2_Rx_IntOut & DDR3_SDRAM_SDMA2_Tx_IntOut & xps_timer_0_Interrupt
 PORT Irq = microblaze_0_Interrupt
END

BEGIN plb_user_logic_32x4096_4cs_10clk
 PARAMETER INSTANCE = plb_user_logic_32x4096_4cs_10clk_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MEM0_BASEADDR = 0x90000000
 PARAMETER C_MEM0_HIGHADDR = 0x9000FFFF
 PARAMETER C_MEM1_BASEADDR = 0x91000000
 PARAMETER C_MEM1_HIGHADDR = 0x9100FFFF
 PARAMETER C_MEM2_BASEADDR = 0x92000000
 PARAMETER C_MEM2_HIGHADDR = 0x9200FFFF
 PARAMETER C_MEM3_BASEADDR = 0x93000000
 PARAMETER C_MEM3_HIGHADDR = 0x9300FFFF
 BUS_INTERFACE SPLB = mb_plb
 PORT user_rd = plb_user_logic_32x4096_4cs_10clk_0_user_rd
 PORT user_clk = plb_user_logic_32x4096_4cs_10clk_0_user_clk
 PORT user_add = plb_user_logic_32x4096_4cs_10clk_0_user_add
 PORT user_wr = plb_user_logic_32x4096_4cs_10clk_0_user_wr
 PORT data_to_user = plb_user_logic_32x4096_4cs_10clk_0_data_to_user
 PORT user_cs = plb_user_logic_32x4096_4cs_10clk_0_user_cs
 PORT data_from_user1 = plb_user_logic_32x4096_4cs_10clk_0_data_from_user1
 PORT data_from_user2 = plb_user_logic_32x4096_4cs_10clk_0_data_from_user2
 PORT data_from_user0 = plb_user_logic_32x4096_4cs_10clk_0_data_from_user0
 PORT data_from_user3 = plb_user_logic_32x4096_4cs_10clk_0_data_from_user3
END

BEGIN chipscope_ila
 PARAMETER INSTANCE = chipscope_ila_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_TRIG0_UNITS = 1
 PARAMETER C_TRIG0_TRIGGER_IN_WIDTH = 32
 PARAMETER C_NUM_DATA_SAMPLES = 1024
 PARAMETER C_TRIG1_UNITS = 1
 PARAMETER C_TRIG1_TRIGGER_IN_WIDTH = 32
 PARAMETER C_TRIG2_UNITS = 1
 PARAMETER C_TRIG2_TRIGGER_IN_WIDTH = 1
 PORT chipscope_ila_control = chipscope_ila_0_icon_control
 PORT TRIG0 = Trace_Instruction
 PORT CLK = clk_100_0000MHzMMCM0
 PORT TRIG1 = Trace_PC
 PORT TRIG2 = Trace_Valid_Instr
END

BEGIN chipscope_icon
 PARAMETER INSTANCE = chipscope_icon_0
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_NUM_CONTROL_PORTS = 1
 PORT control0 = chipscope_ila_0_icon_control
END