system Project Status (07/02/2013 - 14:43:21) | |||
Project File: | v144_z702_npi_v400b.xise | Parser Errors: | No Errors |
Module Name: | system | Implementation State: | Programming File Not Generated |
Target Device: | xc7z020-1clg484 |
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Product Version: | ISE 14.4 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: |
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XPS Reports | [-] | ||||
Report Name | Generated | Errors | Warnings | Infos | |
Platgen Log File | ȭ 7 2 14:34:51 2013 | 0 | 21 Warnings (14 new) | 14 Infos (4 new) | |
Simgen Log File | |||||
BitInit Log File | ȭ 7 2 14:43:18 2013 | 0 | 6 Warnings (4 new) | 5 Infos (2 new) | |
System Log File |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | ȭ 7 2 14:42:39 2013 | |
WebTalk Log File | Current | ȭ 7 2 14:42:55 2013 |