system Project Status (07/02/2013 - 14:43:21)
Project File: v144_z702_npi_v400b.xise Parser Errors: No Errors
Module Name: system_top Implementation State: Programming File Generated
Target Device: xc7z020-1clg484
  • Errors:
No Errors
Product Version:ISE 14.4
  • Warnings:
562 Warnings (421 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log Fileȭ 7 2 14:34:51 2013021 Warnings (14 new)14 Infos (4 new)
Simgen Log File    
BitInit Log Fileȭ 7 2 14:43:18 201306 Warnings (4 new)5 Infos (2 new)
System Log File    
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 4,156 106,400 3%  
    Number used as Flip Flops 4,155      
    Number used as Latches 1      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 3,535 53,200 6%  
    Number used as logic 2,925 53,200 5%  
        Number using O6 output only 2,067      
        Number using O5 output only 106      
        Number using O5 and O6 752      
        Number used as ROM 0      
    Number used as Memory 381 17,400 2%  
        Number used as Dual Port RAM 10      
            Number using O6 output only 2      
            Number using O5 output only 2      
            Number using O5 and O6 6      
        Number used as Single Port RAM 0      
        Number used as Shift Register 371      
            Number using O6 output only 185      
            Number using O5 output only 2      
            Number using O5 and O6 184      
    Number used exclusively as route-thrus 229      
        Number with same-slice register load 197      
        Number with same-slice carry load 32      
        Number with other load 0      
Number of occupied Slices 1,756 13,300 13%  
Number of LUT Flip Flop pairs used 4,930      
    Number with an unused Flip Flop 1,376 4,930 27%  
    Number with an unused LUT 1,395 4,930 28%  
    Number of fully used LUT-FF pairs 2,159 4,930 43%  
    Number of unique control sets 294      
    Number of slice register sites lost
        to control set restrictions
1,153 106,400 1%  
Number of bonded IOBs 0 200 0%  
Number of bonded IOPAD 130 130 100%  
Number of RAMB36E1/FIFO36E1s 11 140 7%  
    Number using RAMB36E1 only 11      
    Number using FIFO36E1 only 0      
Number of RAMB18E1/FIFO18E1s 1 280 1%  
    Number using RAMB18E1 only 1      
    Number using FIFO18E1 only 0      
Number of BUFG/BUFGCTRLs 2 32 6%  
    Number used as BUFGs 2      
    Number used as BUFGCTRLs 0      
Number of IDELAYE2/IDELAYE2_FINEDELAYs 0 200 0%  
Number of ILOGICE2/ILOGICE3/ISERDESE2s 0 200 0%  
Number of ODELAYE2/ODELAYE2_FINEDELAYs 0      
Number of OLOGICE2/OLOGICE3/OSERDESE2s 0 200 0%  
Number of PHASER_IN/PHASER_IN_PHYs 0 16 0%  
Number of PHASER_OUT/PHASER_OUT_PHYs 0 16 0%  
Number of BSCANs 1 4 25%  
Number of BUFHCEs 0 72 0%  
Number of BUFRs 0 16 0%  
Number of CAPTUREs 0 1 0%  
Number of DNA_PORTs 0 1 0%  
Number of DSP48E1s 0 220 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 4 0%  
Number of IN_FIFOs 0 16 0%  
Number of MMCME2_ADVs 0 4 0%  
Number of OUT_FIFOs 0 16 0%  
Number of PHASER_REFs 0 4 0%  
Number of PHY_CONTROLs 0 4 0%  
Number of PLLE2_ADVs 0 4 0%  
Number of PS7s 1 1 100%  
Number of STARTUPs 0 1 0%  
Number of XADCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.27      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentȭ 7 2 12:34:12 201305 Warnings (2 new)119 Infos (3 new)
Translation ReportCurrentȭ 7 2 14:36:19 20130148 Warnings (16 new)5 Infos (2 new)
Map ReportCurrentȭ 7 2 14:40:10 20130136 Warnings (134 new)7 Infos (1 new)
Place and Route ReportCurrentȭ 7 2 14:41:15 20130137 Warnings (135 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportOut of Dateȭ 7 2 12:41:18 2013004 Infos (0 new)
Bitgen ReportCurrentȭ 7 2 14:42:37 20130136 Warnings (134 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentȭ 7 2 14:42:39 2013
WebTalk Log FileCurrentȭ 7 2 14:42:55 2013

Date Generated: 07/02/2013 - 14:43:21