-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 23:24:43 06/30/2013 -- Design Name: -- Module Name: C:/work/2013/npi_simulation/v144_kc705_npi_v400b/tb_bench.vhd -- Project Name: v144_kc705_npi_v400b -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: top -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tb_bench IS END tb_bench; ARCHITECTURE behavior OF tb_bench IS -- Component Declaration for the Unit Under Test (UUT) constant clk_p_period : time := 5000.000000 ps; constant clk_n_period : time := 5000.000000 ps; constant reset_length : time := 80000 ps; COMPONENT top PORT( sm_fan_pwm_net_vcc : OUT std_logic; ddr_memory_we_n : OUT std_logic; ddr_memory_ras_n : OUT std_logic; ddr_memory_odt : OUT std_logic; ddr_memory_dqs_n : INOUT std_logic_vector(0 downto 0); ddr_memory_dqs : INOUT std_logic_vector(0 downto 0); ddr_memory_dq : INOUT std_logic_vector(7 downto 0); ddr_memory_dm : OUT std_logic_vector(0 downto 0); ddr_memory_ddr3_rst : OUT std_logic; ddr_memory_cs_n : OUT std_logic; ddr_memory_clk_n : OUT std_logic; ddr_memory_clk : OUT std_logic; ddr_memory_cke : OUT std_logic; ddr_memory_cas_n : OUT std_logic; ddr_memory_ba : OUT std_logic_vector(2 downto 0); ddr_memory_addr : OUT std_logic_vector(13 downto 0); RS232_Uart_1_sout : OUT std_logic; RS232_Uart_1_sin : IN std_logic; RESET : IN std_logic; LEDs_8Bits_TRI_O : OUT std_logic_vector(7 downto 0); CLK_P : IN std_logic; CLK_N : IN std_logic ); END COMPONENT; component ddr3_model is generic ( ADDR_BITS : INTEGER; BA_BITS : INTEGER; COL_BITS : INTEGER; ROW_BITS : INTEGER; TFAW : INTEGER; TRAS_MIN : INTEGER; TRCD : INTEGER; TRFC_MIN : INTEGER; TRP : INTEGER; TRRD : INTEGER; TRTP : INTEGER; TWTR : INTEGER ); port ( addr : in std_logic_vector(13 downto 0); ba : in std_logic_vector(2 downto 0); cas_n : in std_logic; ck : in std_logic; ck_n : in std_logic; cke : in std_logic; cs_n : in std_logic; dm_tdqs : inout std_logic_vector(0 to 0); dq : inout std_logic_vector(7 downto 0); dqs : inout std_logic_vector(0 to 0); dqs_n : inout std_logic_vector(0 to 0); odt : in std_logic; ras_n : in std_logic; rst_n : in std_logic; we_n : in std_logic; tdqs_n : out std_logic_vector(0 to 0) ); end component; --Inputs signal RS232_Uart_1_sin : std_logic := '0'; signal RESET : std_logic := '0'; signal CLK_P : std_logic := '0'; signal CLK_N : std_logic := '0'; --BiDirs signal ddr_memory_dqs_n : std_logic_vector(0 downto 0); signal ddr_memory_dqs : std_logic_vector(0 downto 0); signal ddr_memory_dq : std_logic_vector(7 downto 0); --Outputs signal sm_fan_pwm_net_vcc : std_logic; signal ddr_memory_we_n : std_logic; signal ddr_memory_ras_n : std_logic; signal ddr_memory_odt : std_logic; signal ddr_memory_dm : std_logic_vector(0 downto 0); signal ddr_memory_ddr3_rst : std_logic; signal ddr_memory_cs_n : std_logic; signal ddr_memory_clk_n : std_logic; signal ddr_memory_clk : std_logic; signal ddr_memory_cke : std_logic; signal ddr_memory_cas_n : std_logic; signal ddr_memory_ba : std_logic_vector(2 downto 0); signal ddr_memory_addr : std_logic_vector(13 downto 0); signal RS232_Uart_1_sout : std_logic; signal LEDs_8Bits_TRI_O : std_logic_vector(7 downto 0); BEGIN dut : top port map ( sm_fan_pwm_net_vcc => sm_fan_pwm_net_vcc, ddr_memory_we_n => ddr_memory_we_n, ddr_memory_ras_n => ddr_memory_ras_n, ddr_memory_odt => ddr_memory_odt, ddr_memory_dqs_n => ddr_memory_dqs_n(0 downto 0), ddr_memory_dqs => ddr_memory_dqs(0 downto 0), ddr_memory_dq => ddr_memory_dq, ddr_memory_dm => ddr_memory_dm(0 downto 0), ddr_memory_ddr3_rst => ddr_memory_ddr3_rst, ddr_memory_cs_n => ddr_memory_cs_n, ddr_memory_clk_n => ddr_memory_clk_n, ddr_memory_clk => ddr_memory_clk, ddr_memory_cke => ddr_memory_cke, ddr_memory_cas_n => ddr_memory_cas_n, ddr_memory_ba => ddr_memory_ba, ddr_memory_addr => ddr_memory_addr, RS232_Uart_1_sout => RS232_Uart_1_sout, RS232_Uart_1_sin => RS232_Uart_1_sin, RESET => RESET, LEDs_8Bits_TRI_O => LEDs_8Bits_TRI_O, CLK_P => CLK_P, CLK_N => CLK_N ); inst_ddr_00 : ddr3_model generic map ( ADDR_BITS => 14, BA_BITS => 3, COL_BITS => 10, ROW_BITS => 14, TFAW => 30000, TRAS_MIN => 35000, TRCD => 13125, TRFC_MIN => 110000, TRP => 13125, TRRD => 6000, TRTP => 7500, TWTR => 7500 ) port map ( addr => ddr_memory_addr, ba => ddr_memory_ba, cas_n => ddr_memory_cas_n, ck => ddr_memory_clk, ck_n => ddr_memory_clk_n, cke => ddr_memory_cke, cs_n => ddr_memory_cs_n, dm_tdqs => ddr_memory_dm(0 downto 0), dq => ddr_memory_dq(7 downto 0), dqs => ddr_memory_dqs(0 downto 0), dqs_n => ddr_memory_dqs_n(0 downto 0), odt => ddr_memory_odt, ras_n => ddr_memory_ras_n, rst_n => ddr_memory_ddr3_rst, we_n => ddr_memory_we_n, tdqs_n => open ); -- Clock generator for CLK_P process begin CLK_P <= '0'; loop wait for (CLK_P_PERIOD/2); CLK_P <= not CLK_P; end loop; end process; -- Clock generator for CLK_N process begin CLK_N <= '1'; loop wait for (CLK_N_PERIOD/2); CLK_N <= not CLK_N; end loop; end process; -- Reset Generator for RESET process begin RESET <= '1'; wait for (RESET_LENGTH); RESET <= not RESET; wait; end process; END;