--Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014 --Date : Fri Sep 19 15:18:21 2014 --Host : XKRHYUKKW7 running 64-bit Service Pack 1 (build 7601) --Command : generate_target system_wrapper.bd --Design : system_wrapper --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_wrapper is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; dip_switches_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); end system_wrapper; architecture STRUCTURE of system_wrapper is component system is port ( DDR_cas_n : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; dip_switches_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 ); FCLK_CLK0 : out STD_LOGIC; In1 : in STD_LOGIC_VECTOR ( 0 to 0 ); In2 : in STD_LOGIC_VECTOR ( 0 to 0 ); In0 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end component system; signal clk : std_logic; signal myint : std_logic_vector(2 downto 0); signal cnt : std_logic_vector(27 downto 0); begin system_i: component system port map ( DDR_addr(14 downto 0) => DDR_addr(14 downto 0), DDR_ba(2 downto 0) => DDR_ba(2 downto 0), DDR_cas_n => DDR_cas_n, DDR_ck_n => DDR_ck_n, DDR_ck_p => DDR_ck_p, DDR_cke => DDR_cke, DDR_cs_n => DDR_cs_n, DDR_dm(3 downto 0) => DDR_dm(3 downto 0), DDR_dq(31 downto 0) => DDR_dq(31 downto 0), DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_odt => DDR_odt, DDR_ras_n => DDR_ras_n, DDR_reset_n => DDR_reset_n, DDR_we_n => DDR_we_n, FCLK_CLK0 => clk, FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), FIXED_IO_ps_clk => FIXED_IO_ps_clk, FIXED_IO_ps_porb => FIXED_IO_ps_porb, FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, In0(0) => myint(0), In1(0) => myint(1), In2(0) => myint(2), dip_switches_4bits_tri_i(3 downto 0) => dip_switches_4bits_tri_i(3 downto 0) ); process(clk) begin if clk'event and clk = '1' then if cnt = x"0000000" then myint(0) <= '1'; elsif cnt = x"0010000" then myint(1) <= '1'; elsif cnt = x"1000000" then myint(2) <= '1'; else myint <= "000"; end if; cnt <= cnt + 1; end if; end process; end STRUCTURE;