-------------------------------------------------------------------------------
-- system_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity system_top is
	port (
			 processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
			 processing_system7_0_PS_SRSTB_pin : in std_logic;
			 processing_system7_0_PS_CLK_pin : in std_logic;
			 processing_system7_0_PS_PORB_pin : in std_logic;
			 processing_system7_0_DDR_Clk : inout std_logic;
			 processing_system7_0_DDR_Clk_n : inout std_logic;
			 processing_system7_0_DDR_CKE : inout std_logic;
			 processing_system7_0_DDR_CS_n : inout std_logic;
			 processing_system7_0_DDR_RAS_n : inout std_logic;
			 processing_system7_0_DDR_CAS_n : inout std_logic;
			 processing_system7_0_DDR_WEB_pin : out std_logic;
			 processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
			 processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
			 processing_system7_0_DDR_ODT : inout std_logic;
			 processing_system7_0_DDR_DRSTB : inout std_logic;
			 processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
			 processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
			 processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
			 processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
			 processing_system7_0_DDR_VRN : inout std_logic;
			 processing_system7_0_DDR_VRP : inout std_logic
		 );
end system_top;

architecture STRUCTURE of system_top is

	component system is
		port (
				 processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
				 processing_system7_0_PS_SRSTB_pin : in std_logic;
				 processing_system7_0_PS_CLK_pin : in std_logic;
				 processing_system7_0_PS_PORB_pin : in std_logic;
				 processing_system7_0_DDR_Clk : inout std_logic;
				 processing_system7_0_DDR_Clk_n : inout std_logic;
				 processing_system7_0_DDR_CKE : inout std_logic;
				 processing_system7_0_DDR_CS_n : inout std_logic;
				 processing_system7_0_DDR_RAS_n : inout std_logic;
				 processing_system7_0_DDR_CAS_n : inout std_logic;
				 processing_system7_0_DDR_WEB_pin : out std_logic;
				 processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
				 processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
				 processing_system7_0_DDR_ODT : inout std_logic;
				 processing_system7_0_DDR_DRSTB : inout std_logic;
				 processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
				 processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
				 processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
				 processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
				 processing_system7_0_DDR_VRN : inout std_logic;
				 processing_system7_0_DDR_VRP : inout std_logic;
				 rd_fifo_data : out std_logic_vector(31 downto 0);
				 rd_fifo_empty : out std_logic;
				 rd_fifo_rd_en : in std_logic;
				 rd_fifo_ready : out std_logic;
				 rd_fifo_clk : in std_logic;
				 rd_fifo_full : out std_logic;
				 wr_fifo_full : out std_logic;
				 wr_fifo_wr_en : in std_logic;
				 wr_fifo_clk : in std_logic;
				 wr_fifo_ready : out std_logic;
				 wr_fifo_data : in std_logic_vector(31 downto 0);
				 wr_fifo_empty : out std_logic;
				 clk_50mhz : out std_logic
			 );
	end component;

	attribute BOX_TYPE : STRING;
	attribute BOX_TYPE of system : component is "user_black_box";

	signal gnd0 : std_logic := '0';
	signal clk : std_logic := '0';
	signal wr_fifo_full, wr_fifo_wr_en, wr_fifo_ready : std_logic := '0';
	signal tx_fifo_full : std_logic;
	signal rd_fifo_data, wr_fifo_data : std_logic_vector(31 downto 0);
	signal rd_fifo_ready, rd_fifo_empty, rd_fifo_rd_en, rd_fifo_full : std_logic;

begin

	system_i : system
	port map (
				 processing_system7_0_MIO => processing_system7_0_MIO,
				 processing_system7_0_PS_SRSTB_pin => processing_system7_0_PS_SRSTB_pin,
				 processing_system7_0_PS_CLK_pin => processing_system7_0_PS_CLK_pin,
				 processing_system7_0_PS_PORB_pin => processing_system7_0_PS_PORB_pin,
				 processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
				 processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
				 processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
				 processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
				 processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
				 processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
				 processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
				 processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
				 processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
				 processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
				 processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
				 processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
				 processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
				 processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
				 processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
				 processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
				 processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
				 --------------------------------------
				 rd_fifo_data => rd_fifo_data,
				 rd_fifo_ready => rd_fifo_ready,
				 rd_fifo_clk => clk,
				 rd_fifo_rd_en => rd_fifo_rd_en,
				 rd_fifo_empty => rd_fifo_empty ,
				 rd_fifo_full => rd_fifo_full,
				 --------------------------------------
				 wr_fifo_ready => wr_fifo_ready ,
				 wr_fifo_empty => open,
				 wr_fifo_data => rd_fifo_data,
				 wr_fifo_clk => clk,
				 wr_fifo_full => wr_fifo_full ,
				 wr_fifo_wr_en => wr_fifo_wr_en,
				 --------------------------------------
				 clk_50mhz =>clk 
			 );

	wr_fifo_wr_en <= '1' when wr_fifo_ready = '1' and rd_fifo_empty = '0' and tx_fifo_full = '0' else '0'; 

	process(clk)
	begin
		if clk'event and clk = '1' then
			if rd_fifo_ready = '1' then
				if rd_fifo_empty = '0' then
					rd_fifo_rd_en <= '1';
				else
					rd_fifo_rd_en <= '0';
				end if;
			else
				rd_fifo_rd_en <= '0';
			end if;
		end if;
	end process;

end architecture STRUCTURE;