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-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:03:40 03/29/2011 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
	PORT(
		fpga_0_RS232_Uart_1_RX_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin : IN std_logic_vector(7 downto 0);
		fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin : IN std_logic;
		fpga_0_clk_1_sys_clk_p_pin : IN std_logic;
		fpga_0_clk_1_sys_clk_n_pin : IN std_logic;
		fpga_0_rst_1_sys_rst_pin : IN std_logic;
		ext_int : IN std_logic;
		fpga_0_LEDs_8Bit_GPIO_IO_pin : INOUT std_logic_vector(0 to 7);
		fpga_0_FLASH_Mem_DQ_pin : INOUT std_logic_vector(0 to 15);
		fpga_0_DDR3_SDRAM_DDR3_DQ_pin : INOUT std_logic_vector(31 downto 0);
		fpga_0_DDR3_SDRAM_DDR3_DQS_pin : INOUT std_logic_vector(3 downto 0);
		fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin : INOUT std_logic_vector(3 downto 0);
		fpga_0_Hard_Ethernet_MAC_MDIO_0_pin : INOUT std_logic;      
		fpga_0_RS232_Uart_1_TX_pin : OUT std_logic;
		fpga_0_FLASH_Mem_A_pin : OUT std_logic_vector(7 to 30);
		fpga_0_FLASH_Mem_OEN_pin : OUT std_logic;
		fpga_0_FLASH_Mem_WEN_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_Clk_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_CE_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_CS_n_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_ODT_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_WE_n_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin : OUT std_logic_vector(2 downto 0);
		fpga_0_DDR3_SDRAM_DDR3_Addr_pin : OUT std_logic_vector(12 downto 0);
		fpga_0_DDR3_SDRAM_DDR3_DM_pin : OUT std_logic_vector(3 downto 0);
		fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin : OUT std_logic_vector(7 downto 0);
		fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_MDC_0_pin : OUT std_logic;
		fpga_0_FLASH_CE_inverter_Res_pin : OUT std_logic
		);
end top;

architecture Behavioral of top is
	COMPONENT system
	PORT(
		fpga_0_RS232_Uart_1_RX_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin : IN std_logic_vector(7 downto 0);
		fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin : IN std_logic;
		fpga_0_clk_1_sys_clk_p_pin : IN std_logic;
		fpga_0_clk_1_sys_clk_n_pin : IN std_logic;
		fpga_0_rst_1_sys_rst_pin : IN std_logic;
		ext_int : IN std_logic;
		data_from_user1 : IN std_logic_vector(0 to 31);
		data_from_user2 : IN std_logic_vector(0 to 31);
		data_from_user0 : IN std_logic_vector(0 to 31);
		data_from_user3 : IN std_logic_vector(0 to 31);    
		fpga_0_LEDs_8Bit_GPIO_IO_pin : INOUT std_logic_vector(0 to 7);
		fpga_0_FLASH_Mem_DQ_pin : INOUT std_logic_vector(0 to 15);
		fpga_0_DDR3_SDRAM_DDR3_DQ_pin : INOUT std_logic_vector(31 downto 0);
		fpga_0_DDR3_SDRAM_DDR3_DQS_pin : INOUT std_logic_vector(3 downto 0);
		fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin : INOUT std_logic_vector(3 downto 0);
		fpga_0_Hard_Ethernet_MAC_MDIO_0_pin : INOUT std_logic;      
		fpga_0_RS232_Uart_1_TX_pin : OUT std_logic;
		fpga_0_FLASH_Mem_A_pin : OUT std_logic_vector(7 to 30);
		fpga_0_FLASH_Mem_OEN_pin : OUT std_logic;
		fpga_0_FLASH_Mem_WEN_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_Clk_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_CE_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_CS_n_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_ODT_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_WE_n_pin : OUT std_logic;
		fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin : OUT std_logic_vector(2 downto 0);
		fpga_0_DDR3_SDRAM_DDR3_Addr_pin : OUT std_logic_vector(12 downto 0);
		fpga_0_DDR3_SDRAM_DDR3_DM_pin : OUT std_logic_vector(3 downto 0);
		fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin : OUT std_logic_vector(7 downto 0);
		fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_MDC_0_pin : OUT std_logic;
		fpga_0_FLASH_CE_inverter_Res_pin : OUT std_logic;
		user_rd : OUT std_logic;
		user_clk : OUT std_logic;
		user_add : OUT std_logic_vector(0 to 11);
		user_wr : OUT std_logic;
		data_to_user : OUT std_logic_vector(0 to 31);
		user_cs : OUT std_logic_vector(0 to 3)
		);
	END COMPONENT;

attribute box_type : string;
attribute box_type of system : component is "user_black_box";

	signal reg0, reg1, reg2 : std_logic_vector(0 to 31);
	signal user_add : std_logic_vector(0 to 11);
	signal user_cs: std_logic_vector(0 to 3);
	signal data_from_user0, data_from_user1,data_from_user2, data_from_user3 : std_logic_vector(0 to 31); 
	signal data_to_user : std_logic_vector(0 to 31); 
	signal user_rd, user_wr, user_clk : std_logic;

begin

	Inst_system: system PORT MAP(
		fpga_0_RS232_Uart_1_RX_pin =>fpga_0_RS232_Uart_1_RX_pin  ,
		fpga_0_RS232_Uart_1_TX_pin =>fpga_0_RS232_Uart_1_TX_pin  ,
		fpga_0_LEDs_8Bit_GPIO_IO_pin =>fpga_0_LEDs_8Bit_GPIO_IO_pin  ,
		fpga_0_FLASH_Mem_A_pin =>fpga_0_FLASH_Mem_A_pin  ,
		fpga_0_FLASH_Mem_OEN_pin =>fpga_0_FLASH_Mem_OEN_pin  ,
		fpga_0_FLASH_Mem_WEN_pin =>fpga_0_FLASH_Mem_WEN_pin  ,
		fpga_0_FLASH_Mem_DQ_pin =>fpga_0_FLASH_Mem_DQ_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_Clk_pin =>fpga_0_DDR3_SDRAM_DDR3_Clk_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin =>fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_CE_pin =>fpga_0_DDR3_SDRAM_DDR3_CE_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_CS_n_pin =>fpga_0_DDR3_SDRAM_DDR3_CS_n_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_ODT_pin => fpga_0_DDR3_SDRAM_DDR3_ODT_pin ,
		fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin =>fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin =>fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_WE_n_pin =>fpga_0_DDR3_SDRAM_DDR3_WE_n_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin =>fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_Addr_pin =>fpga_0_DDR3_SDRAM_DDR3_Addr_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_DQ_pin =>fpga_0_DDR3_SDRAM_DDR3_DQ_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_DM_pin =>fpga_0_DDR3_SDRAM_DDR3_DM_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin =>fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_DQS_pin =>fpga_0_DDR3_SDRAM_DDR3_DQS_pin  ,
		fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin =>fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin  ,
		fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin =>fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin  ,
		fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin =>fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin  ,
		fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin =>fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin  ,
		fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin =>fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin  ,
		fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin =>fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin  ,
		fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin =>fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin  ,
		fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin =>fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin  ,
		fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin =>fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin  ,
		fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin =>fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin  ,
		fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin =>fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin  ,
		fpga_0_Hard_Ethernet_MAC_MDC_0_pin =>fpga_0_Hard_Ethernet_MAC_MDC_0_pin  ,
		fpga_0_Hard_Ethernet_MAC_MDIO_0_pin =>fpga_0_Hard_Ethernet_MAC_MDIO_0_pin  ,
		fpga_0_clk_1_sys_clk_p_pin =>fpga_0_clk_1_sys_clk_p_pin  ,
		fpga_0_clk_1_sys_clk_n_pin =>fpga_0_clk_1_sys_clk_n_pin  ,
		fpga_0_rst_1_sys_rst_pin =>fpga_0_rst_1_sys_rst_pin  ,
		fpga_0_FLASH_CE_inverter_Res_pin =>fpga_0_FLASH_CE_inverter_Res_pin  ,
		ext_int =>ext_int  ,
		user_rd =>user_rd  ,
		user_clk =>user_clk  ,
		user_add => user_add ,
		user_wr =>user_wr  ,
		data_to_user =>data_to_user  ,
		user_cs =>user_cs  ,
		data_from_user1 =>data_from_user1  ,
		data_from_user2 =>data_from_user2  ,
		data_from_user0 =>data_from_user0  ,
		data_from_user3 =>data_from_user3  
	);


	process(user_clk)
	begin
		if user_clk'event and user_clk = '1' then
			if user_cs(0) = '1' then
				if user_rd = '1' then
					case user_add is
						when x"000" => data_from_user0 <= reg0;
						when x"001" => data_from_user0 <= reg1;
						when x"002" => data_from_user0 <= reg2;
						when x"003" => data_from_user0 <= x"12345678"; 	-- pre define
						when others => null;
					end case;
				end if;

				if user_wr = '1' then
					case user_add is
						when x"000" => reg0 <= data_to_user;
						when x"001" => reg1 <= data_to_user;
						when x"002" => reg2 <= data_to_user;
						when others => null;
					end case;
				end if;
			end if;
		end if;
	end process;


end Behavioral;