-------------------------------------------------------------------------------
-- top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity top is
	port (
		sm_fan_pwm_net_vcc : out std_logic;
		ddr_memory_we_n : out std_logic;
		ddr_memory_ras_n : out std_logic;
		ddr_memory_odt : out std_logic;
		ddr_memory_dqs_n : inout std_logic_vector(0 to 0);
		ddr_memory_dqs : inout std_logic_vector(0 to 0);
		ddr_memory_dq : inout std_logic_vector(7 downto 0);
		ddr_memory_dm : out std_logic_vector(0 to 0);
		ddr_memory_ddr3_rst : out std_logic;
		ddr_memory_cs_n : out std_logic;
		ddr_memory_clk_n : out std_logic;
		ddr_memory_clk : out std_logic;
		ddr_memory_cke : out std_logic;
		ddr_memory_cas_n : out std_logic;
		ddr_memory_ba : out std_logic_vector(2 downto 0);
		ddr_memory_addr : out std_logic_vector(13 downto 0);
		RS232_Uart_1_sout : out std_logic;
		RS232_Uart_1_sin : in std_logic;
		RESET : in std_logic;
		LEDs_8Bits_TRI_O : out std_logic_vector(7 downto 0);
		CLK_P : in std_logic;
		CLK_N : in std_logic
	);
end top;

architecture STRUCTURE of top is

	component system is
	port (
		sm_fan_pwm_net_vcc : out std_logic;
		ddr_memory_we_n : out std_logic;
		ddr_memory_ras_n : out std_logic;
		ddr_memory_odt : out std_logic;
		ddr_memory_dqs_n : inout std_logic_vector(0 to 0);
		ddr_memory_dqs : inout std_logic_vector(0 to 0);
		ddr_memory_dq : inout std_logic_vector(7 downto 0);
		ddr_memory_dm : out std_logic_vector(0 to 0);
		ddr_memory_ddr3_rst : out std_logic;
		ddr_memory_cs_n : out std_logic;
		ddr_memory_clk_n : out std_logic;
		ddr_memory_clk : out std_logic;
		ddr_memory_cke : out std_logic;
		ddr_memory_cas_n : out std_logic;
		ddr_memory_ba : out std_logic_vector(2 downto 0);
		ddr_memory_addr : out std_logic_vector(13 downto 0);
		RS232_Uart_1_sout : out std_logic;
		RS232_Uart_1_sin : in std_logic;
		RESET : in std_logic;
		LEDs_8Bits_TRI_O : out std_logic_vector(7 downto 0);
		CLK_P : in std_logic;
		CLK_N : in std_logic;
		dummy_out : out std_logic_vector(31 downto 0);
		dummy_in : in std_logic_vector(31 downto 0);
		clk_100mhz : out std_logic;
		rd_fifo_empty : out std_logic;
		rd_fifo_data : out std_logic_vector(31 downto 0);
		rd_fifo_full : out std_logic;
		rd_fifo_clk : in std_logic;
		rd_fifo_rd_en : in std_logic;
		rd_fifo_ready : out std_logic;
		wr_fifo_full : out std_logic;
		wr_fifo_empty : out std_logic;
		wr_fifo_clk : in std_logic;
		wr_fifo_ready : out std_logic;
		wr_fifo_data : in std_logic_vector(31 downto 0);
		wr_fifo_wr_en : in std_logic
	);
	end component;

	attribute BOX_TYPE : STRING;
	attribute BOX_TYPE of system : component is "user_black_box";

	signal gnd0 : std_logic := '0';
	signal clk : std_logic := '0';
	signal wr_fifo_full, wr_fifo_wr_en, wr_fifo_ready : std_logic := '0';
	signal rd_fifo_data, wr_fifo_data : std_logic_vector(31 downto 0);
	signal rd_fifo_ready, rd_fifo_empty, rd_fifo_rd_en, rd_fifo_full : std_logic;
	signal wr_fifo_wr_en_d0, wr_fifo_wr_en_d1 : std_logic;

begin

	system_i : system
	port map (
		sm_fan_pwm_net_vcc => sm_fan_pwm_net_vcc,
		ddr_memory_we_n => ddr_memory_we_n,
		ddr_memory_ras_n => ddr_memory_ras_n,
		ddr_memory_odt => ddr_memory_odt,
		ddr_memory_dqs_n => ddr_memory_dqs_n(0 to 0),
		ddr_memory_dqs => ddr_memory_dqs(0 to 0),
		ddr_memory_dq => ddr_memory_dq,
		ddr_memory_dm => ddr_memory_dm(0 to 0),
		ddr_memory_ddr3_rst => ddr_memory_ddr3_rst,
		ddr_memory_cs_n => ddr_memory_cs_n,
		ddr_memory_clk_n => ddr_memory_clk_n,
		ddr_memory_clk => ddr_memory_clk,
		ddr_memory_cke => ddr_memory_cke,
		ddr_memory_cas_n => ddr_memory_cas_n,
		ddr_memory_ba => ddr_memory_ba,
		ddr_memory_addr => ddr_memory_addr,
		RS232_Uart_1_sout => RS232_Uart_1_sout,
		RS232_Uart_1_sin => RS232_Uart_1_sin,
		RESET => RESET,
		LEDs_8Bits_TRI_O => LEDs_8Bits_TRI_O,
		CLK_P => CLK_P,
		CLK_N => CLK_N,
		--------------------------------------
		rd_fifo_data => rd_fifo_data,
		rd_fifo_ready => rd_fifo_ready,
		rd_fifo_clk => clk,
		rd_fifo_rd_en => rd_fifo_rd_en,
		rd_fifo_empty => rd_fifo_empty ,
		rd_fifo_full => rd_fifo_full,
		--------------------------------------
		wr_fifo_ready => wr_fifo_ready ,
		wr_fifo_empty => open,
		wr_fifo_data => rd_fifo_data,
		wr_fifo_clk => clk,
		wr_fifo_full => wr_fifo_full ,
		wr_fifo_wr_en => wr_fifo_wr_en_d1,
		--------------------------------------
		dummy_in => rd_fifo_data, 
		dummy_out => open, 
		clk_100mhz => clk);

	wr_fifo_wr_en <= '1' when wr_fifo_ready = '1' and rd_fifo_empty = '0' and wr_fifo_full = '0' else '0'; 

	process(clk)
	begin
		if clk'event and clk = '1' then
			wr_fifo_wr_en_d0 <= wr_fifo_wr_en; 
			wr_fifo_wr_en_d1 <= wr_fifo_wr_en_d0; 
		end if;
	end process;

	process(clk)
	begin
		if clk'event and clk = '1' then
			if rd_fifo_ready = '1' then
				if rd_fifo_empty = '0' then
					rd_fifo_rd_en <= '1';
				else
					rd_fifo_rd_en <= '0';
				end if;
			else
				rd_fifo_rd_en <= '0';
			end if;
		end if;
	end process;

end architecture STRUCTURE;