-------------------------------------------------------------------------------
-- system_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity system_top is
  port (
    RS232_Uart_1_sout : out std_logic;
    RS232_Uart_1_sin : in std_logic;
    RESET : in std_logic;
    CLK_P : in std_logic;
    CLK_N : in std_logic
  );
end system_top;

architecture STRUCTURE of system_top is

  component system is
    port (
      RS232_Uart_1_sout : out std_logic;
      RS232_Uart_1_sin : in std_logic;
      RESET : in std_logic;
      CLK_P : in std_logic;
      CLK_N : in std_logic;
      data_from_user2 : in std_logic_vector(31 downto 0);
      data_from_user0 : in std_logic_vector(31 downto 0);
      user_cs : out std_logic_vector(3 downto 0);
      user_rd : out std_logic;
      data_from_user1 : in std_logic_vector(31 downto 0);
      user_wr : out std_logic;
      data_to_user : out std_logic_vector(31 downto 0);
      user_clk : out std_logic;
      user_add : out std_logic_vector(11 downto 0);
      data_from_user3 : in std_logic_vector(31 downto 0)
    );
  end component;

 attribute BOX_TYPE : STRING;
 attribute BOX_TYPE of system : component is "user_black_box";
	signal user_rd, user_wr, clk : std_logic;
	signal reg0, reg1, gnd32, data_from_user0, data_to_user : std_logic_vector(31 downto 0) := (others => '0');
	signal user_cs : std_logic_vector(3 downto 0);
	signal user_add : std_logic_vector(11 downto 0);

begin

  system_i : system
    port map (
      RS232_Uart_1_sout => RS232_Uart_1_sout,
      RS232_Uart_1_sin => RS232_Uart_1_sin,
      RESET => RESET,
      CLK_P => CLK_P,
      CLK_N => CLK_N,
      data_from_user3 => gnd32,
      user_cs => user_cs,
      data_from_user2 => gnd32,
      data_from_user1 => gnd32,
      user_wr => user_wr,
      data_to_user => data_to_user,
      user_rd => user_rd,
      user_add => user_add,
      user_clk => clk,
      data_from_user0 => data_from_user0
    );

	process(clk)
	begin
		if clk'event and clk = '1' then
			if user_cs(0) = '1' then
				if user_rd = '1' then
					case user_add is
						when x"000" => data_from_user0 <= reg0;
						when x"001" => data_from_user0 <= reg1;
						when x"002" => data_from_user0 <= x"12345678";
						when others => null;
					end case;
				end if;

				if user_wr = '1' then
					case user_add is
						when x"000" => reg0 <= data_to_user;
						when x"001" => reg1 <= data_to_user;
						when others => null;
					end case;
				end if;
			end if;
		end if;
	end process;


end architecture STRUCTURE;