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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:09:48 08/27/2009 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
  generic 
  ( 
			  C_MEM_WIDTH : integer              := 32 
  );
	PORT(
		sys_clk_pin : IN std_logic;
		sys_rst_pin : IN std_logic;    
		--------------------------------------------------
		tx : OUT std_logic;
		rx : IN std_logic;
		--------------------------------------------------
		clk745mhz : IN std_logic;
		--------------------------------------------------
		gpio_o :  OUT std_logic_vector(31 downto 0);
		gpio_in :  IN std_logic_vector(31 downto 0);
		int_o : OUT std_logic;
		ddr2_dqs_n : INOUT std_logic_vector((C_MEM_WIDTH/8 - 1) downto 0);
		ddr2_dqs : INOUT std_logic_vector((C_MEM_WIDTH/8 - 1) downto 0);
		ddr2_dq : INOUT std_logic_vector((C_MEM_WIDTH - 1) downto 0);      
		ddr2_dm : OUT std_logic_vector((C_MEM_WIDTH/8 - 1) downto 0);
		ddr2_a : OUT std_logic_vector(12 downto 0);
		ddr2_ba : OUT std_logic_vector(1 downto 0);
		ddr2_we_n : OUT std_logic;
		ddr2_cas_n : OUT std_logic;
		ddr2_ras_n : OUT std_logic;
		ddr2_odt : OUT std_logic;
		ddr2_cs_n : OUT std_logic;
		ddr2_cke : OUT std_logic;
		ddr2_ck_n : OUT std_logic_vector(1 downto 0);
		ddr2_ck : OUT std_logic_vector(1 downto 0));
end top;

architecture Behavioral of top is
	COMPONENT system
	PORT(
		rx : IN std_logic;
		gpio_in : IN std_logic_vector(31 downto 0);
		int_o : OUT std_logic;
		sys_clk_pin : IN std_logic;
		sys_rst_pin : IN std_logic;
		npi_rd_fifo_rd_en : IN std_logic;
		npi_wr_fifo_clk : IN std_logic;
		npi_wr_fifo_wr_en : IN std_logic;
		npi_wr_fifo_data : IN std_logic_vector(31 downto 0);
		npi_rd_fifo_clk : IN std_logic;
		ddr2_dq : INOUT std_logic_vector((C_MEM_WIDTH - 1)downto 0);
		ddr2_dqs : INOUT std_logic_vector((C_MEM_WIDTH/8 - 1)  downto 0);
		ddr2_dqs_n : INOUT std_logic_vector((C_MEM_WIDTH/8 - 1)  downto 0);      
		tx : OUT std_logic;
		ddr2_ck : OUT std_logic_vector(1 downto 0);
		ddr2_ck_n : OUT std_logic_vector(1 downto 0);
		ddr2_cke : OUT std_logic;
		ddr2_cs_n : OUT std_logic;
		ddr2_odt : OUT std_logic;
		ddr2_ras_n : OUT std_logic;
		ddr2_cas_n : OUT std_logic;
		ddr2_we_n : OUT std_logic;
		ddr2_ba : OUT std_logic_vector(1 downto 0);
		ddr2_a : OUT std_logic_vector(12 downto 0);
		ddr2_dm : OUT std_logic_vector(3 downto 0);
		gpio_o : OUT std_logic_vector(0 to 31);
		npi_rd_fifo_empty : OUT std_logic;
		npi_rd_fifo_data : OUT std_logic_vector(31 downto 0);
		npi_rd_fifo_full : OUT std_logic;
		npi_wr_fifo_empty : OUT std_logic;
		npi_wr_fifo_full : OUT std_logic;
		npi_rd_ready : OUT std_logic;
		npi_wr_ready : OUT std_logic;
		--
		npi_rd_fifo_empty_1 : OUT std_logic;
		npi_rd_fifo_data_1 : OUT std_logic_vector(31 downto 0);
		npi_rd_fifo_full_1 : OUT std_logic;
		npi_wr_fifo_empty_1 : OUT std_logic;
		npi_wr_fifo_full_1 : OUT std_logic;
		npi_rd_ready_1 : OUT std_logic;
		npi_wr_ready_1 : OUT std_logic;
		npi_rd_fifo_rd_en_1 : IN std_logic;
		npi_wr_fifo_clk_1 : IN std_logic;
		npi_wr_fifo_wr_en_1 : IN std_logic;
		npi_wr_fifo_data_1 : IN std_logic_vector(31 downto 0);
		npi_rd_fifo_clk_1 : IN std_logic);    
	END COMPONENT;

attribute box_type : string;
attribute box_type of system : component is "user_black_box";

	signal npi_wr_fifo_wr_en, npi_rd_fifo_rd_en, npi_wr_ready_1, npi_rd_fifo_empty : std_logic := '0';
	signal data_in_out : std_logic_vector(31 downto 0);
	signal gnd0 : std_logic := '0';
	signal gnd32 : std_logic_vector(31 downto 0) := x"00000000";

begin
	uut : system PORT MAP(
		sys_clk_pin =>sys_clk_pin  ,
		sys_rst_pin =>sys_rst_pin  ,
		ddr2_dqs_n =>ddr2_dqs_n  ,
		ddr2_dqs =>ddr2_dqs  ,
		ddr2_dm =>ddr2_dm  ,
		ddr2_dq =>ddr2_dq  ,
		ddr2_a =>ddr2_a  ,
		ddr2_ba =>ddr2_ba  ,
		ddr2_we_n =>ddr2_we_n  ,
		ddr2_cas_n =>ddr2_cas_n  ,
		ddr2_ras_n =>ddr2_ras_n  ,
		ddr2_odt =>ddr2_odt  ,
		ddr2_cs_n =>ddr2_cs_n  ,
		ddr2_cke =>ddr2_cke  ,
		ddr2_ck_n =>ddr2_ck_n  ,
		ddr2_ck =>ddr2_ck,  
		rx => rx,
		tx => tx,
		gpio_in => gpio_in, 
		int_o => int_o, 
        gpio_o => gpio_o,  
		--------------------------------------
		npi_rd_fifo_clk => clk745mhz,
		npi_rd_fifo_empty => npi_rd_fifo_empty,
		npi_rd_fifo_rd_en => npi_rd_fifo_rd_en,
		npi_rd_fifo_data => data_in_out,
		npi_rd_fifo_full => open,
		npi_rd_ready => open,
		--
		npi_wr_fifo_clk => clk745mhz,
		npi_wr_ready => open,
		npi_wr_fifo_wr_en => gnd0,
		npi_wr_fifo_data => gnd32,
		npi_wr_fifo_empty => open,
		npi_wr_fifo_full => open,  
		--------------------------------------
		npi_rd_fifo_clk_1 => clk745mhz,
		npi_rd_ready_1 => open,
		npi_rd_fifo_empty_1 => open,
		npi_rd_fifo_rd_en_1 => gnd0,
		npi_rd_fifo_data_1 => gnd32,
		npi_rd_fifo_full_1 => open,
		---
		npi_wr_fifo_clk_1 => clk745mhz,
		npi_wr_ready_1 => npi_wr_ready_1,
		npi_wr_fifo_wr_en_1 => npi_wr_fifo_wr_en,
		npi_wr_fifo_data_1 => data_in_out,
		npi_wr_fifo_empty_1 => open,
		npi_wr_fifo_full_1 => open);

	npi_rd_fifo_rd_en <= not npi_rd_fifo_empty;
	process(clk745mhz)
	begin 
		if clk745mhz'event and clk745mhz = '1' then
			if npi_wr_ready_1 = '1' then
				npi_wr_fifo_wr_en <= npi_rd_fifo_rd_en; 
			end if;
		end if;
	end process;
end Behavioral;