# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
# Sat Dec 26 08:59:34 2009
# Target Board:  Avnet Avnet V5FXT Evaluation Board Rev B
# Family:    virtex5
# Device:    xc5vfx30t
# Package:   ff665
# Speed Grade:  -1
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 125.0
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT rx = fpga_0_RS232_RX_pin, DIR = I
 PORT tx = fpga_0_RS232_TX_pin, DIR = O
 PORT ddr2_ck = fpga_0_DDR2_SDRAM_16Mx32_DDR2_Clk_pin, DIR = O, VEC = [1:0]
 PORT ddr2_ck_n = fpga_0_DDR2_SDRAM_16Mx32_DDR2_Clk_n_pin, DIR = O, VEC = [1:0]
 PORT ddr2_cke = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CE_pin, DIR = O
 PORT ddr2_cs_n = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_n_pin, DIR = O
 PORT ddr2_odt = fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin, DIR = O
 PORT ddr2_ras_n = fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_n_pin, DIR = O
 PORT ddr2_cas_n = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_n_pin, DIR = O
 PORT ddr2_we_n = fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_n_pin, DIR = O
 PORT ddr2_ba = fpga_0_DDR2_SDRAM_16Mx32_DDR2_BankAddr_pin, DIR = O, VEC = [1:0]
 PORT ddr2_a = fpga_0_DDR2_SDRAM_16Mx32_DDR2_Addr_pin, DIR = O, VEC = [12:0]
 PORT ddr2_dm = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin, DIR = O, VEC = [3:0]
 PORT ddr2_dq = ddr2_dq, DIR = IO, VEC = [31:0]
 PORT ddr2_dqs = ddr2_dqs, DIR = IO, VEC = [3:0]
 PORT ddr2_dqs_n = ddr2_dqs_n, DIR = IO, VEC = [3:0]
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT gpio_o = xps_gpio_0_GPIO_IO_O, DIR = O, VEC = [0:31]
 PORT gpio_in = xps_gpio_0_GPIO2_IO_I, DIR = I, VEC = [31:0]
 PORT int_o = xps_gpio_0_IP2INTC_Irpt, DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH
# #
 PORT npi_rd_fifo_empty = npi_user_if_0_RD_FIFO_EMPTY, DIR = O
 PORT npi_rd_fifo_rd_en = npi_user_if_0_RD_FIFO_RD_EN, DIR = I
 PORT npi_rd_fifo_data = npi_user_if_0_RD_FIFO_DATA, DIR = O, VEC = [31:0]
 PORT npi_rd_fifo_full = npi_user_if_0_RD_FIFO_FULL, DIR = O
 PORT npi_wr_fifo_clk = npi_user_if_0_WR_FIFO_CLK, DIR = I
 PORT npi_wr_fifo_wr_en = npi_user_if_0_WR_FIFO_WR_EN, DIR = I
 PORT npi_wr_fifo_data = npi_user_if_0_WR_FIFO_DATA, DIR = I, VEC = [31:0]
 PORT npi_wr_fifo_empty = npi_user_if_0_WR_FIFO_EMPTY, DIR = O
 PORT npi_wr_fifo_full = npi_user_if_0_WR_FIFO_FULL, DIR = O
 PORT npi_rd_fifo_clk = npi_user_if_0_RD_FIFO_CLK, DIR = I
 PORT NPI_RD_READY = npi_user_if_0_NPI_RD_READY, DIR = O
 PORT NPI_WR_READY = npi_user_if_0_NPI_WR_READY, DIR = O
# #
 PORT npi_wr_fifo_full_1 = npi_user_if_1_WR_FIFO_FULL, DIR = O
 PORT npi_wr_fifo_emptY_1 = npi_user_if_1_WR_FIFO_EMPTY, DIR = O
 PORT npi_wr_fifo_data_1 = npi_user_if_1_WR_FIFO_DATA, DIR = I, VEC = [31:0]
 PORT npi_wr_fifo_wr_eN_1 = npi_user_if_1_WR_FIFO_WR_EN, DIR = I
 PORT npi_wr_fifo_clk_1 = npi_user_if_1_WR_FIFO_CLK, DIR = I
 PORT npi_rd_ready_1 = npi_user_if_1_NPI_RD_READY, DIR = O
 PORT npi_rd_fifo_full_1 = npi_user_if_1_RD_FIFO_FULL, DIR = O
 PORT npi_rd_fifo_data_1 = npi_user_if_1_RD_FIFO_DATA, DIR = O, VEC = [31:0]
 PORT npi_rd_fifo_rd_eN_1 = npi_user_if_1_RD_FIFO_RD_EN, DIR = I
 PORT npi_rd_fifo_emptY_1 = npi_user_if_1_RD_FIFO_EMPTY, DIR = O
 PORT npi_rd_fifo_clk_1 = npi_user_if_1_RD_FIFO_CLK, DIR = I
 PORT npi_wr_ready_1 = npi_user_if_1_NPI_WR_READY, DIR = O


# #
# PORT npi_rd_fifo_rd_en_4 = npi_user_if_4_RD_FIFO_RD_EN, DIR = I
# PORT npi_rd_fifo_empty_4 = npi_user_if_4_RD_FIFO_EMPTY, DIR = O
# PORT npi_rd_fifo_full_4 = npi_user_if_4_RD_FIFO_FULL, DIR = O
# PORT npi_rd_fifo_data_4 = npi_user_if_4_RD_FIFO_DATA, DIR = O, VEC = [31:0]
# PORT npi_wr_fifo_clk_4 = npi_user_if_4_WR_FIFO_CLK, DIR = I
# PORT npi_rd_ready_4 = npi_user_if_4_NPI_RD_READY, DIR = O
# PORT npi_wr_fifo_data_4 = npi_user_if_4_WR_FIFO_DATA, DIR = I, VEC = [31:0]
# PORT npi_wr_fifo_wr_en_4 = npi_user_if_4_WR_FIFO_WR_EN, DIR = I
# PORT npi_wr_fifo_full_4 = npi_user_if_4_WR_FIFO_FULL, DIR = O
# PORT npi_wr_fifo_empty_4 = npi_user_if_4_WR_FIFO_EMPTY, DIR = O
# PORT npi_wr_ready_4 = npi_user_if_4_NPI_WR_READY, DIR = O
# PORT npi_rd_fifo_clk_4 = npi_user_if_4_RD_FIFO_CLK, DIR = I
# #
# PORT npi_rd_fifo_rd_en_5 = npi_user_if_5_RD_FIFO_RD_EN, DIR = I
# PORT npi_rd_fifo_empty_5 = npi_user_if_5_RD_FIFO_EMPTY, DIR = O
# PORT npi_rd_fifo_full_5 = npi_user_if_5_RD_FIFO_FULL, DIR = O
# PORT npi_rd_fifo_data_5 = npi_user_if_5_RD_FIFO_DATA, DIR = O, VEC = [31:0]
# PORT npi_wr_fifo_clk_5 = npi_user_if_5_WR_FIFO_CLK, DIR = I
# PORT npi_rd_ready_5 = npi_user_if_5_NPI_RD_READY, DIR = O
# PORT npi_wr_fifo_data_5 = npi_user_if_5_WR_FIFO_DATA, DIR = I, VEC = [31:0]
# PORT npi_wr_fifo_wr_en_5 = npi_user_if_5_WR_FIFO_WR_EN, DIR = I
# PORT npi_wr_fifo_full_5 = npi_user_if_5_WR_FIFO_FULL, DIR = O
# PORT npi_wr_fifo_empty_5 = npi_user_if_5_WR_FIFO_EMPTY, DIR = O
# PORT npi_wr_ready_5 = npi_user_if_5_NPI_WR_READY, DIR = O
# PORT npi_rd_fifo_clk_5 = npi_user_if_5_RD_FIFO_CLK, DIR = I
# PORT clk100mhz = clk_100_0000MHzPLL0, DIR = O, SIGIS = CLK, CLK_FREQ = 100000000
BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0x40000000
 PARAMETER C_ICACHE_HIGHADDR = 0x43ffffff
 PARAMETER C_CACHE_BYTE_SIZE = 64
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_DCACHE_BASEADDR = 0x40000000
 PARAMETER C_DCACHE_HIGHADDR = 0x43ffffff
 PARAMETER C_DCACHE_BYTE_SIZE = 64
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 PARAMETER HW_VER = 8.00.a
 PARAMETER C_USE_ICACHE = 0
 PARAMETER C_USE_DCACHE = 0
 PARAMETER C_USE_FPU = 1
 PARAMETER C_FPU_EXCEPTION = 1
 PARAMETER C_DPLB_BUS_EXCEPTION = 1
 PARAMETER C_IPLB_BUS_EXCEPTION = 1
 PARAMETER C_ILL_OPCODE_EXCEPTION = 1
 PARAMETER C_UNALIGNED_EXCEPTIONS = 1
 PARAMETER C_OPCODE_0x0_ILLEGAL = 1
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
 BUS_INTERFACE IXCL = microblaze_0_IXCL
 BUS_INTERFACE DXCL = microblaze_0_DXCL
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 PORT MB_RESET = mb_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.05.a
 PORT PLB_Clk = clk_100_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_100_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_100_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000FFFF
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000FFFF
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER C_BAUDRATE = 921600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_RX_pin
 PORT TX = fpga_0_RS232_TX_pin
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR2_SDRAM_16Mx32
 PARAMETER C_NUM_IDELAYCTRL = 2
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y1-IDELAYCTRL_X0Y2
 PARAMETER C_MEM_PARTNO = mt47h16m16-5e
 PARAMETER C_MEM_CLK_WIDTH = 2
 PARAMETER C_MEM_DATA_WIDTH = 32
 PARAMETER C_DDR2_DQSN_ENABLE = 1
 PARAMETER C_NUM_PORTS = 5
 PARAMETER C_PIM0_BASETYPE = 1
 PARAMETER C_PIM1_BASETYPE = 1
 PARAMETER C_PIM2_BASETYPE = 4
 PARAMETER C_PIM3_BASETYPE = 4
# PARAMETER HW_VER = 5.04.a
 PARAMETER HW_VER = 6.02.a
 PARAMETER C_MPMC_BASEADDR = 0x50000000
 PARAMETER C_MPMC_HIGHADDR = 0x53FFFFFF
 PARAMETER C_SKIP_SIM_INIT_DELAY = 1
# PARAMETER C_PIM0_DATA_WIDTH = 64
# PARAMETER C_PIM1_DATA_WIDTH = 64
# PARAMETER C_PIM2_DATA_WIDTH = 64
# PARAMETER C_PIM3_DATA_WIDTH = 64
# PARAMETER C_PI2_RD_FIFO_TYPE = BRAM
# PARAMETER C_PI3_WR_FIFO_TYPE = BRAM
# PARAMETER C_PIM4_BASETYPE = 4
# PARAMETER C_PIM5_BASETYPE = 4
 PARAMETER C_PIM6_BASETYPE = 0
 PARAMETER C_PIM7_BASETYPE = 0
 PARAMETER C_PIM4_BASETYPE = 2
 PARAMETER C_PI2_WR_FIFO_TYPE = DISABLED
 PARAMETER C_PI3_RD_FIFO_TYPE = DISABLED
 BUS_INTERFACE XCL0 = microblaze_0_IXCL
 BUS_INTERFACE XCL1 = microblaze_0_DXCL
 BUS_INTERFACE MPMC_PIM2 = npi_user_if_0_XIL_NPI
 BUS_INTERFACE MPMC_PIM3 = npi_user_if_1_XIL_NPI
 BUS_INTERFACE SPLB4 = mb_plb
 PORT MPMC_Clk0 = clk_200_0000MHzPLL0
 PORT MPMC_Clk0_DIV2 = clk_100_0000MHzPLL0
 PORT MPMC_Clk90 = clk_200_0000MHz90PLL0
 PORT MPMC_Clk_200MHz = clk_200_0000MHz
 PORT MPMC_Rst = sys_periph_reset
 PORT DDR2_Clk = fpga_0_DDR2_SDRAM_16Mx32_DDR2_Clk_pin
 PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_16Mx32_DDR2_Clk_n_pin
 PORT DDR2_CE = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CE_pin
 PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_n_pin
 PORT DDR2_ODT = fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin
 PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_n_pin
 PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_n_pin
 PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_n_pin
 PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_16Mx32_DDR2_BankAddr_pin
 PORT DDR2_Addr = fpga_0_DDR2_SDRAM_16Mx32_DDR2_Addr_pin
 PORT DDR2_DQ = ddr2_dq
 PORT DDR2_DM = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin
 PORT DDR2_DQS = ddr2_dqs
 PORT DDR2_DQS_n = ddr2_dqs_n
END

# BEGIN clock_generator
# PARAMETER INSTANCE = clock_generator_0
# PARAMETER C_EXT_RESET_HIGH = 1
# PARAMETER C_CLKIN_FREQ = 100000000
# PARAMETER C_CLKOUT0_FREQ = 125000000
# PARAMETER C_CLKOUT0_PHASE = 90
# PARAMETER C_CLKOUT0_GROUP = PLL0
# PARAMETER C_CLKOUT0_BUF = TRUE
# PARAMETER C_CLKOUT1_FREQ = 125000000
# PARAMETER C_CLKOUT1_PHASE = 0
# PARAMETER C_CLKOUT1_GROUP = PLL0
# PARAMETER C_CLKOUT1_BUF = TRUE
# PARAMETER C_CLKOUT2_FREQ = 200000000
# PARAMETER C_CLKOUT2_PHASE = 0
# PARAMETER C_CLKOUT2_GROUP = NONE
# PARAMETER C_CLKOUT2_BUF = TRUE
# PARAMETER C_CLKOUT3_FREQ = 62500000
# PARAMETER C_CLKOUT3_PHASE = 0
# PARAMETER C_CLKOUT3_GROUP = PLL0
# PARAMETER C_CLKOUT3_BUF = TRUE
# PARAMETER HW_VER = 3.02.a
# PORT CLKIN = dcm_clk_s
# PORT CLKOUT0 = clk_125_0000MHz90PLL0
# PORT CLKOUT1 = clk_125_0000MHzPLL0
# PORT CLKOUT2 = clk_200_0000MHz
# PORT CLKOUT3 = clk_62_5000MHzPLL0
# PORT RST = sys_rst_s
# PORT LOCKED = Dcm_all_locked
# END
BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 200000000
 PARAMETER C_CLKOUT0_PHASE = 90
 PARAMETER C_CLKOUT0_GROUP = PLL0
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = PLL0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 200000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = NONE
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT3_FREQ = 100000000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = PLL0
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_FAMILY = virtex5
 PORT CLKIN = dcm_clk_s
 PORT CLKOUT0 = clk_200_0000MHz90PLL0
 PORT CLKOUT1 = clk_200_0000MHzPLL0
 PORT CLKOUT2 = clk_200_0000MHz
 PORT CLKOUT3 = clk_100_0000MHzPLL0
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
END

BEGIN mdm
 PARAMETER INSTANCE = mdm_0
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 3.00.a
 PORT Slowest_sync_clk = clk_100_0000MHzPLL0
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Dcm_locked = Dcm_all_locked
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_gpio
 PARAMETER INSTANCE = xps_gpio_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x30000000
 PARAMETER C_HIGHADDR = 0x3000FFFF
 PARAMETER C_GPIO_WIDTH = 32
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_IS_DUAL = 1
 PARAMETER C_ALL_INPUTS_2 = 1
 BUS_INTERFACE SPLB = mb_plb
 PORT GPIO_IO_O = xps_gpio_0_GPIO_IO_O
 PORT GPIO2_IO_I = xps_gpio_0_GPIO2_IO_I
 PORT IP2INTC_Irpt = xps_gpio_0_IP2INTC_Irpt
END

BEGIN npi_user_if
 PARAMETER INSTANCE = npi_user_if_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000FFFF
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE XIL_NPI = npi_user_if_0_XIL_NPI
 PORT XIL_NPI_Clk = clk_200_0000MHzPLL0
 PORT XIL_NPI_Rst = sys_periph_reset
 PORT RD_FIFO_EMPTY = npi_user_if_0_RD_FIFO_EMPTY
 PORT RD_FIFO_RD_EN = npi_user_if_0_RD_FIFO_RD_EN
 PORT RD_FIFO_DATA = npi_user_if_0_RD_FIFO_DATA
 PORT RD_FIFO_FULL = npi_user_if_0_RD_FIFO_FULL
 PORT WR_FIFO_CLK = npi_user_if_0_WR_FIFO_CLK
 PORT WR_FIFO_WR_EN = npi_user_if_0_WR_FIFO_WR_EN
 PORT WR_FIFO_DATA = npi_user_if_0_WR_FIFO_DATA
 PORT WR_FIFO_EMPTY = npi_user_if_0_WR_FIFO_EMPTY
 PORT WR_FIFO_FULL = npi_user_if_0_WR_FIFO_FULL
 PORT RD_FIFO_CLK = npi_user_if_0_RD_FIFO_CLK
 PORT NPI_RD_READY = npi_user_if_0_NPI_RD_READY
 PORT NPI_WR_READY = npi_user_if_0_NPI_WR_READY
END

BEGIN npi_user_if
 PARAMETER INSTANCE = npi_user_if_1
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x41000000
 PARAMETER C_HIGHADDR = 0x4100FFFF
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE XIL_NPI = npi_user_if_1_XIL_NPI
 PORT XIL_NPI_Clk = clk_200_0000MHzPLL0
 PORT XIL_NPI_Rst = sys_periph_reset
 PORT WR_FIFO_FULL = npi_user_if_1_WR_FIFO_FULL
 PORT WR_FIFO_EMPTY = npi_user_if_1_WR_FIFO_EMPTY
 PORT WR_FIFO_DATA = npi_user_if_1_WR_FIFO_DATA
 PORT WR_FIFO_WR_EN = npi_user_if_1_WR_FIFO_WR_EN
 PORT WR_FIFO_CLK = npi_user_if_1_WR_FIFO_CLK
 PORT NPI_RD_READY = npi_user_if_1_NPI_RD_READY
 PORT RD_FIFO_FULL = npi_user_if_1_RD_FIFO_FULL
 PORT RD_FIFO_DATA = npi_user_if_1_RD_FIFO_DATA
 PORT RD_FIFO_RD_EN = npi_user_if_1_RD_FIFO_RD_EN
 PORT RD_FIFO_EMPTY = npi_user_if_1_RD_FIFO_EMPTY
 PORT RD_FIFO_CLK = npi_user_if_1_RD_FIFO_CLK
 PORT NPI_WR_READY = npi_user_if_1_NPI_WR_READY
END