system Project Status (08/06/2013 - 02:34:15)
Project File: v144_sp605_user_logic.xise Parser Errors: No Errors
Module Name: system Implementation State: Programming File Not Generated
Target Device: xc6slx45t-3fgg484
  • Errors:
 
Product Version:ISE 14.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log Fileȭ 8 6 02:27:14 201304 Warnings (3 new)24 Infos (14 new)
Simgen Log File    
BitInit Log Fileȭ 8 6 02:34:14 201301 Warning (1 new)10 Infos (10 new)
System Log File    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentȭ 8 6 02:33:46 2013

Date Generated: 08/06/2013 - 02:34:15