Device Utilization Summary | [-] |
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers |
1,871 |
54,576 |
3% |
|
Number used as Flip Flops |
1,864 |
|
|
|
Number used as Latches |
0 |
|
|
|
Number used as Latch-thrus |
0 |
|
|
|
Number used as AND/OR logics |
7 |
|
|
|
Number of Slice LUTs |
2,463 |
27,288 |
9% |
|
Number used as logic |
2,259 |
27,288 |
8% |
|
Number using O6 output only |
1,811 |
|
|
|
Number using O5 output only |
45 |
|
|
|
Number using O5 and O6 |
403 |
|
|
|
Number used as ROM |
0 |
|
|
|
Number used as Memory |
142 |
6,408 |
2% |
|
Number used as Dual Port RAM |
64 |
|
|
|
Number using O6 output only |
0 |
|
|
|
Number using O5 output only |
0 |
|
|
|
Number using O5 and O6 |
64 |
|
|
|
Number used as Single Port RAM |
0 |
|
|
|
Number used as Shift Register |
78 |
|
|
|
Number using O6 output only |
23 |
|
|
|
Number using O5 output only |
1 |
|
|
|
Number using O5 and O6 |
54 |
|
|
|
Number used exclusively as route-thrus |
62 |
|
|
|
Number with same-slice register load |
57 |
|
|
|
Number with same-slice carry load |
4 |
|
|
|
Number with other load |
1 |
|
|
|
Number of occupied Slices |
837 |
6,822 |
12% |
|
Number of MUXCYs used |
492 |
13,644 |
3% |
|
Number of LUT Flip Flop pairs used |
2,722 |
|
|
|
Number with an unused Flip Flop |
1,003 |
2,722 |
36% |
|
Number with an unused LUT |
259 |
2,722 |
9% |
|
Number of fully used LUT-FF pairs |
1,460 |
2,722 |
53% |
|
Number of unique control sets |
147 |
|
|
|
Number of slice register sites lost to control set restrictions |
572 |
54,576 |
1% |
|
Number of bonded IOBs |
5 |
296 |
1% |
|
Number of LOCed IOBs |
5 |
5 |
100% |
|
Number of RAMB16BWERs |
16 |
116 |
13% |
|
Number of RAMB8BWERs |
0 |
232 |
0% |
|
Number of BUFIO2/BUFIO2_2CLKs |
1 |
32 |
3% |
|
Number used as BUFIO2s |
1 |
|
|
|
Number used as BUFIO2_2CLKs |
0 |
|
|
|
Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
Number of BUFG/BUFGMUXs |
2 |
16 |
12% |
|
Number used as BUFGs |
2 |
|
|
|
Number used as BUFGMUX |
0 |
|
|
|
Number of DCM/DCM_CLKGENs |
0 |
8 |
0% |
|
Number of ILOGIC2/ISERDES2s |
0 |
376 |
0% |
|
Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
376 |
0% |
|
Number of OLOGIC2/OSERDES2s |
0 |
376 |
0% |
|
Number of BSCANs |
1 |
4 |
25% |
|
Number of BUFHs |
0 |
256 |
0% |
|
Number of BUFPLLs |
0 |
8 |
0% |
|
Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
Number of DSP48A1s |
3 |
58 |
5% |
|
Number of GTPA1_DUALs |
0 |
2 |
0% |
|
Number of ICAPs |
0 |
1 |
0% |
|
Number of MCBs |
0 |
2 |
0% |
|
Number of PCIE_A1s |
0 |
1 |
0% |
|
Number of PCILOGICSEs |
0 |
2 |
0% |
|
Number of PLL_ADVs |
1 |
4 |
25% |
|
Number of PMVs |
0 |
1 |
0% |
|
Number of STARTUPs |
0 |
1 |
0% |
|
Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
Average Fanout of Non-Clock Nets |
4.35 |
|
|
|