system Project Status (08/06/2013 - 02:34:15)
Project File: v144_sp605_user_logic.xise Parser Errors: No Errors
Module Name: system_top Implementation State: Programming File Generated
Target Device: xc6slx45t-3fgg484
  • Errors:
No Errors
Product Version:ISE 14.4
  • Warnings:
61 Warnings (61 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log Fileȭ 8 6 02:27:14 201304 Warnings (3 new)24 Infos (14 new)
Simgen Log File    
BitInit Log Fileȭ 8 6 02:34:14 201301 Warning (1 new)10 Infos (10 new)
System Log File    
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 1,871 54,576 3%  
    Number used as Flip Flops 1,864      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 7      
Number of Slice LUTs 2,463 27,288 9%  
    Number used as logic 2,259 27,288 8%  
        Number using O6 output only 1,811      
        Number using O5 output only 45      
        Number using O5 and O6 403      
        Number used as ROM 0      
    Number used as Memory 142 6,408 2%  
        Number used as Dual Port RAM 64      
            Number using O6 output only 0      
            Number using O5 output only 0      
            Number using O5 and O6 64      
        Number used as Single Port RAM 0      
        Number used as Shift Register 78      
            Number using O6 output only 23      
            Number using O5 output only 1      
            Number using O5 and O6 54      
    Number used exclusively as route-thrus 62      
        Number with same-slice register load 57      
        Number with same-slice carry load 4      
        Number with other load 1      
Number of occupied Slices 837 6,822 12%  
Number of MUXCYs used 492 13,644 3%  
Number of LUT Flip Flop pairs used 2,722      
    Number with an unused Flip Flop 1,003 2,722 36%  
    Number with an unused LUT 259 2,722 9%  
    Number of fully used LUT-FF pairs 1,460 2,722 53%  
    Number of unique control sets 147      
    Number of slice register sites lost
        to control set restrictions
572 54,576 1%  
Number of bonded IOBs 5 296 1%  
    Number of LOCed IOBs 5 5 100%  
Number of RAMB16BWERs 16 116 13%  
Number of RAMB8BWERs 0 232 0%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 8 0%  
Number of ILOGIC2/ISERDES2s 0 376 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 376 0%  
Number of OLOGIC2/OSERDES2s 0 376 0%  
Number of BSCANs 1 4 25%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 3 58 5%  
Number of GTPA1_DUALs 0 2 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCIE_A1s 0 1 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 4 25%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.35      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentȭ 8 6 02:28:24 201301 Warning (1 new)43 Infos (43 new)
Translation ReportCurrentȭ 8 6 02:29:53 201304 Warnings (4 new)1 Info (1 new)
Map ReportCurrentȭ 8 6 02:31:44 2013018 Warnings (18 new)10 Infos (10 new)
Place and Route ReportCurrentȭ 8 6 02:32:44 2013020 Warnings (20 new)2 Infos (2 new)
Power Report     
Post-PAR Static Timing ReportCurrentȭ 8 6 02:33:03 2013004 Infos (4 new)
Bitgen ReportCurrentȭ 8 6 02:33:45 2013018 Warnings (18 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentȭ 8 6 02:33:46 2013

Date Generated: 08/06/2013 - 02:34:15