system Project Status (08/06/2013 - 02:34:15) | |||
Project File: | v144_sp605_user_logic.xise | Parser Errors: | No Errors |
Module Name: | system | Implementation State: | Programming File Not Generated |
Target Device: | xc6slx45t-3fgg484 |
|
|
Product Version: | ISE 14.4 |
|
|
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: |
|
XPS Reports | [-] | ||||
Report Name | Generated | Errors | Warnings | Infos | |
Platgen Log File | ȭ 8 6 02:27:14 2013 | 0 | 4 Warnings (3 new) | 24 Infos (14 new) | |
Simgen Log File | |||||
BitInit Log File | ȭ 8 6 02:34:14 2013 | 0 | 1 Warning (1 new) | 10 Infos (10 new) | |
System Log File |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Log File | Current | ȭ 8 6 02:33:46 2013 |