--Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014 --Date : Sat Jun 21 13:12:48 2014 --Host : XKRHYUKKW7 running 64-bit Service Pack 1 (build 7601) --Command : generate_target system_wrapper.bd --Design : system_wrapper --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_wrapper is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC ); end system_wrapper; architecture STRUCTURE of system_wrapper is component system is port ( DDR_cas_n : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; data_from_user0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); user_clk : out STD_LOGIC; user_wr : out STD_LOGIC; user_rd : out STD_LOGIC; user_cs : out STD_LOGIC; data_to_user : out STD_LOGIC_VECTOR ( 31 downto 0 ); user_add : out STD_LOGIC_VECTOR ( 16 downto 0 ) ); end component system; signal user_rd, user_wr, clk : std_logic; signal reg0, reg1, gnd32, data_from_user0, data_to_user : std_logic_vector(31 downto 0); signal user_cs : std_logic; signal user_add : std_logic_vector(16 downto 0); begin system_i: system port map ( DDR_addr(14 downto 0) => DDR_addr(14 downto 0), DDR_ba(2 downto 0) => DDR_ba(2 downto 0), DDR_cas_n => DDR_cas_n, DDR_ck_n => DDR_ck_n, DDR_ck_p => DDR_ck_p, DDR_cke => DDR_cke, DDR_cs_n => DDR_cs_n, DDR_dm(3 downto 0) => DDR_dm(3 downto 0), DDR_dq(31 downto 0) => DDR_dq(31 downto 0), DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_odt => DDR_odt, DDR_ras_n => DDR_ras_n, DDR_reset_n => DDR_reset_n, DDR_we_n => DDR_we_n, FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), FIXED_IO_ps_clk => FIXED_IO_ps_clk, FIXED_IO_ps_porb => FIXED_IO_ps_porb, FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, data_from_user0(31 downto 0) => data_from_user0(31 downto 0), data_to_user(31 downto 0) => data_to_user(31 downto 0), user_add(16 downto 0) => user_add(16 downto 0), user_clk => clk, user_cs => user_cs, user_rd => user_rd, user_wr => user_wr); process(clk) begin if clk'event and clk = '1' then if user_cs = '1' then if user_rd = '1' then case user_add is when '0' & x"0000" => data_from_user0 <= reg0; when '0' & x"0001" => data_from_user0 <= reg1; when '0' & x"0002" => data_from_user0 <= x"12345678"; when others => null; end case; end if; if user_wr = '1' then case user_add is when '0' & x"000" => reg0 <= data_to_user; when '0' & x"001" => reg1 <= data_to_user; when others => null; end case; end if; end if; end if; end process; end STRUCTURE;