################################################################
# This is a generated script based on design: design_1
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2015.4
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source design_1_script.tcl

# If you do not already have a project created,
# you can create a project using the following command:
#    create_project project_1 myproj -part xc7z020clg484-1
#    set_property BOARD_PART xilinx.com:zc702:part0:1.2 [current_project]

# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
   puts "ERROR: Please open or create a project!"
   return 1
}



# CHANGE DESIGN NAME HERE
set design_name design_1

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   puts "INFO: Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   puts "INFO: Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   puts "INFO: Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   puts $errMsg
   return $nRet
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]

  # Create ports
  set m00_axi_error [ create_bd_port -dir O m00_axi_error ]
  set m00_axi_error_1 [ create_bd_port -dir O m00_axi_error_1 ]
  set m00_axi_init_axi_txn [ create_bd_port -dir I m00_axi_init_axi_txn ]
  set m00_axi_init_axi_txn_1 [ create_bd_port -dir I m00_axi_init_axi_txn_1 ]
  set m00_axi_txn_done [ create_bd_port -dir O m00_axi_txn_done ]
  set m00_axi_txn_done2 [ create_bd_port -dir O m00_axi_txn_done2 ]
  set m00_axi_txn_done2_1 [ create_bd_port -dir O m00_axi_txn_done2_1 ]
  set m00_axi_txn_done_1 [ create_bd_port -dir O m00_axi_txn_done_1 ]

  # Create instance: axi_mem_intercon, and set properties
  set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ]
  set_property -dict [ list \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {1} \
 ] $axi_mem_intercon

  # Create instance: axi_mem_intercon1, and set properties
  set axi_mem_intercon1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon1 ]
  set_property -dict [ list \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {1} \
 ] $axi_mem_intercon1

  # Create instance: myMaster_0, and set properties
  set myMaster_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:myMaster:1.0 myMaster_0 ]
  set_property -dict [ list \
CONFIG.C_M00_AXI_TARGET_SLAVE_BASE_ADDR {0x10000000} \
 ] $myMaster_0

  # Create instance: myMaster_1, and set properties
  set myMaster_1 [ create_bd_cell -type ip -vlnv xilinx.com:user:myMaster:1.0 myMaster_1 ]
  set_property -dict [ list \
CONFIG.C_M00_AXI_TARGET_SLAVE_BASE_ADDR {0x10000000} \
 ] $myMaster_1

  # Create instance: processing_system7_0, and set properties
  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
  set_property -dict [ list \
CONFIG.PCW_USE_M_AXI_GP0 {0} \
CONFIG.PCW_USE_S_AXI_HP0 {1} \
CONFIG.PCW_USE_S_AXI_HP1 {0} \
CONFIG.PCW_USE_S_AXI_HP2 {1} \
CONFIG.preset {ZC702} \
 ] $processing_system7_0

  # Create instance: rst_processing_system7_0_50M, and set properties
  set rst_processing_system7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_processing_system7_0_50M ]

  # Create interface connections
  connect_bd_intf_net -intf_net axi_mem_intercon1_M00_AXI [get_bd_intf_pins axi_mem_intercon1/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP2]
  connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
  connect_bd_intf_net -intf_net myMaster_0_M00_AXI [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins myMaster_0/M00_AXI]
  connect_bd_intf_net -intf_net myMaster_1_M00_AXI [get_bd_intf_pins axi_mem_intercon1/S00_AXI] [get_bd_intf_pins myMaster_1/M00_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]

  # Create port connections
  connect_bd_net -net m00_axi_init_axi_txn_1 [get_bd_ports m00_axi_init_axi_txn] [get_bd_pins myMaster_0/m00_axi_init_axi_txn]
  connect_bd_net -net m00_axi_init_axi_txn_1_1 [get_bd_ports m00_axi_init_axi_txn_1] [get_bd_pins myMaster_1/m00_axi_init_axi_txn]
  connect_bd_net -net myMaster_0_m00_axi_error [get_bd_ports m00_axi_error] [get_bd_pins myMaster_0/m00_axi_error]
  connect_bd_net -net myMaster_0_m00_axi_txn_done [get_bd_ports m00_axi_txn_done] [get_bd_pins myMaster_0/m00_axi_txn_done]
  connect_bd_net -net myMaster_0_m00_axi_txn_done2 [get_bd_ports m00_axi_txn_done2] [get_bd_pins myMaster_0/m00_axi_txn_done2]
  connect_bd_net -net myMaster_1_m00_axi_error [get_bd_ports m00_axi_error_1] [get_bd_pins myMaster_1/m00_axi_error]
  connect_bd_net -net myMaster_1_m00_axi_txn_done [get_bd_ports m00_axi_txn_done_1] [get_bd_pins myMaster_1/m00_axi_txn_done]
  connect_bd_net -net myMaster_1_m00_axi_txn_done2 [get_bd_ports m00_axi_txn_done2_1] [get_bd_pins myMaster_1/m00_axi_txn_done2]
  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_mem_intercon1/ACLK] [get_bd_pins axi_mem_intercon1/M00_ACLK] [get_bd_pins axi_mem_intercon1/S00_ACLK] [get_bd_pins myMaster_0/m00_axi_aclk] [get_bd_pins myMaster_1/m00_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] [get_bd_pins rst_processing_system7_0_50M/slowest_sync_clk]
  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_processing_system7_0_50M/ext_reset_in]
  connect_bd_net -net rst_processing_system7_0_50M_interconnect_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins axi_mem_intercon1/ARESETN] [get_bd_pins rst_processing_system7_0_50M/interconnect_aresetn]
  connect_bd_net -net rst_processing_system7_0_50M_peripheral_aresetn [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon1/M00_ARESETN] [get_bd_pins axi_mem_intercon1/S00_ARESETN] [get_bd_pins myMaster_0/m00_axi_aresetn] [get_bd_pins myMaster_1/m00_axi_aresetn] [get_bd_pins rst_processing_system7_0_50M/peripheral_aresetn]

  # Create address segments
  create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces myMaster_0/M00_AXI] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM
  create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces myMaster_1/M00_AXI] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM

  # Perform GUI Layout
  regenerate_bd_layout -layout_string {
   guistr: "# # String gsaved with Nlview 6.5.5  2015-06-26 bk=1.3371 VDI=38 GEI=35 GUI=JA:1.6
#  -string -flagsOSRD
preplace port DDR -pg 1 -y 60 -defaultsOSRD
preplace port m00_axi_txn_done_1 -pg 1 -y 590 -defaultsOSRD
preplace port m00_axi_error -pg 1 -y 370 -defaultsOSRD
preplace port m00_axi_init_axi_txn -pg 1 -y 510 -defaultsOSRD
preplace port m00_axi_txn_done2_1 -pg 1 -y 610 -defaultsOSRD
preplace port m00_axi_error_1 -pg 1 -y 630 -defaultsOSRD
preplace port FIXED_IO -pg 1 -y 80 -defaultsOSRD
preplace port m00_axi_txn_done2 -pg 1 -y 350 -defaultsOSRD
preplace port m00_axi_txn_done -pg 1 -y 330 -defaultsOSRD
preplace port m00_axi_init_axi_txn_1 -pg 1 -y 620 -defaultsOSRD
preplace inst myMaster_0 -pg 1 -lvl 3 -y 340 -defaultsOSRD
preplace inst myMaster_1 -pg 1 -lvl 3 -y 600 -defaultsOSRD
preplace inst rst_processing_system7_0_50M -pg 1 -lvl 1 -y 180 -defaultsOSRD
preplace inst axi_mem_intercon1 -pg 1 -lvl 2 -y 370 -defaultsOSRD
preplace inst axi_mem_intercon -pg 1 -lvl 2 -y 130 -defaultsOSRD
preplace inst processing_system7_0 -pg 1 -lvl 3 -y 130 -defaultsOSRD
preplace netloc processing_system7_0_DDR 1 3 1 NJ
preplace netloc myMaster_1_m00_axi_error 1 3 1 NJ
preplace netloc myMaster_1_m00_axi_txn_done 1 3 1 NJ
preplace netloc rst_processing_system7_0_50M_interconnect_aresetn 1 1 1 360
preplace netloc myMaster_1_m00_axi_txn_done2 1 3 1 NJ
preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 4 20 490 NJ 490 NJ 490 1150
preplace netloc axi_mem_intercon_M00_AXI 1 2 1 680
preplace netloc m00_axi_init_axi_txn_1_1 1 0 3 NJ 620 NJ 620 NJ
preplace netloc rst_processing_system7_0_50M_peripheral_aresetn 1 1 2 370 500 700
preplace netloc processing_system7_0_FIXED_IO 1 3 1 NJ
preplace netloc myMaster_0_m00_axi_txn_done2 1 3 1 NJ
preplace netloc myMaster_0_m00_axi_txn_done 1 3 1 NJ
preplace netloc myMaster_0_M00_AXI 1 1 3 350 10 NJ 10 1160
preplace netloc processing_system7_0_FCLK_CLK0 1 0 4 20 90 350 520 690 260 1130
preplace netloc myMaster_1_M00_AXI 1 1 3 380 250 NJ 250 1140
preplace netloc axi_mem_intercon1_M00_AXI 1 2 1 680
preplace netloc myMaster_0_m00_axi_error 1 3 1 NJ
preplace netloc m00_axi_init_axi_txn_1 1 0 3 NJ 510 NJ 510 NJ
levelinfo -pg 1 0 190 530 920 1180 -top 0 -bot 680
",
}

  # Restore current instance
  current_bd_instance $oldCurInst

  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""


puts "\n\nWARNING: This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."