# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.4 Build EDK_O.87xd
# Wed Feb 08 05:51:07 2012
# Target Board:  xilinx.com ml605 Rev D
# Family:    virtex6
# Device:    xc6vlx240t
# Package:   ff1156
# Speed Grade:  -1
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O
 PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I
 PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
 PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
 PORT axi_uartlite_0_RX_pin = axi_uartlite_0_RX, DIR = I
 PORT axi_uartlite_0_TX_pin = axi_uartlite_0_TX, DIR = O
 PORT bram_add_0 = axi_user_bram_ctrl_8kbyte_0_bram_add, DIR = O, VEC = [10:0]
 PORT bram_we_0 = axi_user_bram_ctrl_8kbyte_0_bram_we, DIR = O, VEC = [3:0]
 PORT bram_din_0 = axi_user_bram_ctrl_8kbyte_0_bram_din, DIR = O, VEC = [31:0]
 PORT bram_clk_0 = axi_user_bram_ctrl_8kbyte_0_bram_clk, DIR = O
 PORT bram_cs_0 = axi_user_bram_ctrl_8kbyte_0_bram_cs, DIR = O
 PORT bram_dout_0 = axi_user_bram_ctrl_8kbyte_0_bram_dout, DIR = I, VEC = [31:0]
 PORT bram_add_1 = axi_user_bram_ctrl_8kbyte_1_bram_add, DIR = O, VEC = [10:0]
 PORT bram_clk_1 = axi_user_bram_ctrl_8kbyte_1_bram_clk, DIR = O
 PORT bram_cs_1 = axi_user_bram_ctrl_8kbyte_1_bram_cs, DIR = O
 PORT bram_din_1 = axi_user_bram_ctrl_8kbyte_1_bram_din, DIR = O, VEC = [31:0]
 PORT bram_dout_1 = axi_user_bram_ctrl_8kbyte_1_bram_dout, DIR = I, VEC = [31:0]
 PORT bram_we_1 = axi_user_bram_ctrl_8kbyte_1_bram_we, DIR = O, VEC = [3:0]


BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
 PORT MB_Reset = proc_sys_reset_0_MB_Reset
 PORT Slowest_sync_clk = clk_100_0000MHz
 PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
 PORT Ext_Reset_In = RESET
 PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_1_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_1_i_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = microblaze_1_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_1_i_bram_ctrl_2_microblaze_1_bram_block
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_1_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_1_d_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = microblaze_1_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_1_d_bram_ctrl_2_microblaze_1_bram_block
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_1_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = microblaze_1_i_bram_ctrl_2_microblaze_1_bram_block
 BUS_INTERFACE PORTB = microblaze_1_d_bram_ctrl_2_microblaze_1_bram_block
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_1
 PARAMETER HW_VER = 8.20.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0X00000000
 PARAMETER C_ICACHE_HIGHADDR = 0X3FFFFFFF
 PARAMETER C_USE_ICACHE = 0
 PARAMETER C_ICACHE_ALWAYS_USED = 0
 PARAMETER C_DCACHE_BASEADDR = 0X00000000
 PARAMETER C_DCACHE_HIGHADDR = 0X3FFFFFFF
 PARAMETER C_USE_DCACHE = 0
 PARAMETER C_DCACHE_ALWAYS_USED = 0
 BUS_INTERFACE ILMB = microblaze_1_ilmb
 BUS_INTERFACE DLMB = microblaze_1_dlmb
 BUS_INTERFACE M_AXI_DP = axi4lite_1
 BUS_INTERFACE DEBUG = microblaze_1_debug
 PORT MB_RESET = proc_sys_reset_0_MB_Reset
 PORT CLK = clk_100_0000MHz
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = microblaze_0_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = microblaze_0_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
 BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 8.20.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0X00000000
 PARAMETER C_ICACHE_HIGHADDR = 0X3FFFFFFF
 PARAMETER C_USE_ICACHE = 0
 PARAMETER C_ICACHE_ALWAYS_USED = 0
 PARAMETER C_DCACHE_BASEADDR = 0X00000000
 PARAMETER C_DCACHE_HIGHADDR = 0X3FFFFFFF
 PARAMETER C_USE_DCACHE = 0
 PARAMETER C_DCACHE_ALWAYS_USED = 0
 BUS_INTERFACE ILMB = microblaze_0_ilmb
 BUS_INTERFACE DLMB = microblaze_0_dlmb
 BUS_INTERFACE M_AXI_DP = axi4lite_0
 BUS_INTERFACE DEBUG = microblaze_0_debug
 PORT MB_RESET = proc_sys_reset_0_MB_Reset
 PORT CLK = clk_100_0000MHz
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_USE_UART = 0
 PARAMETER C_MB_DBG_PORTS = 2
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
 BUS_INTERFACE MBDEBUG_1 = microblaze_1_debug
 PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT S_AXI_ACLK = clk_100_0000MHz
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_CLKIN_FREQ = 200000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_GROUP = NONE
 PORT LOCKED = proc_sys_reset_0_Dcm_locked
 PORT CLKOUT0 = clk_100_0000MHz
 PORT RST = RESET
 PORT CLKIN = CLK
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_0
 PARAMETER HW_VER = 1.05.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
 PORT INTERCONNECT_ACLK = clk_100_0000MHz
END

BEGIN axi_uartlite
 PARAMETER INSTANCE = RS232_Uart_0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 1
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHz
 PORT TX = RS232_Uart_1_sout
 PORT RX = RS232_Uart_1_sin
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_1
 PARAMETER HW_VER = 1.05.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ACLK = clk_100_0000MHz
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE S_AXI = axi4lite_1
 PORT RX = axi_uartlite_0_RX
 PORT TX = axi_uartlite_0_TX
 PORT S_AXI_ACLK = clk_100_0000MHz
END

BEGIN axi_user_bram_ctrl_8kbyte
 PARAMETER INSTANCE = axi_user_bram_ctrl_8kbyte_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_S_AXI_MEM0_BASEADDR = 0x77600000
 PARAMETER C_S_AXI_MEM0_HIGHADDR = 0x7760ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHz
 PORT bram_add = axi_user_bram_ctrl_8kbyte_0_bram_add
 PORT bram_we = axi_user_bram_ctrl_8kbyte_0_bram_we
 PORT bram_din = axi_user_bram_ctrl_8kbyte_0_bram_din
 PORT bram_clk = axi_user_bram_ctrl_8kbyte_0_bram_clk
 PORT bram_cs = axi_user_bram_ctrl_8kbyte_0_bram_cs
 PORT bram_dout = axi_user_bram_ctrl_8kbyte_0_bram_dout
END

BEGIN axi_user_bram_ctrl_8kbyte
 PARAMETER INSTANCE = axi_user_bram_ctrl_8kbyte_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_S_AXI_MEM0_BASEADDR = 0x77600000
 PARAMETER C_S_AXI_MEM0_HIGHADDR = 0x7760ffff
 BUS_INTERFACE S_AXI = axi4lite_1
 PORT S_AXI_ACLK = clk_100_0000MHz
 PORT bram_add = axi_user_bram_ctrl_8kbyte_1_bram_add
 PORT bram_clk = axi_user_bram_ctrl_8kbyte_1_bram_clk
 PORT bram_cs = axi_user_bram_ctrl_8kbyte_1_bram_cs
 PORT bram_din = axi_user_bram_ctrl_8kbyte_1_bram_din
 PORT bram_dout = axi_user_bram_ctrl_8kbyte_1_bram_dout
 PORT bram_we = axi_user_bram_ctrl_8kbyte_1_bram_we
END

BEGIN axi_timer_1ms
 PARAMETER INSTANCE = axi_timer_1ms_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x7a000000
 PARAMETER C_HIGHADDR = 0x7a00ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHz
END

BEGIN axi_timer_1ms
 PARAMETER INSTANCE = axi_timer_1ms_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x7a000000
 PARAMETER C_HIGHADDR = 0x7a00ffff
 BUS_INTERFACE S_AXI = axi4lite_1
 PORT S_AXI_ACLK = clk_100_0000MHz
END