-------------------------------------------------------------------------------
-- system_tb.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

-- START USER CODE (Do not remove this line)

-- User: Put your libraries here. Code in this
--       section will not be overwritten.

-- END USER CODE (Do not remove this line)

entity system_tb is
end system_tb;

architecture STRUCTURE of system_tb is

  constant fpga_0_clk_1_sys_clk_pin_PERIOD : time := 20000.000000 ps;
  constant fpga_0_rst_1_sys_rst_pin_LENGTH : time := 320000 ps;

  component system is
    port (
      fpga_0_Generic_External_Memory_Mem_A_pin : out std_logic_vector(0 to 31);
      fpga_0_Generic_External_Memory_Mem_RPN_pin : out std_logic;
      fpga_0_Generic_External_Memory_Mem_CEN_pin : out std_logic;
      fpga_0_Generic_External_Memory_Mem_OEN_pin : out std_logic;
      fpga_0_Generic_External_Memory_Mem_WEN_pin : out std_logic;
      fpga_0_Generic_External_Memory_Mem_BEN_pin : out std_logic_vector(0 to 1);
      fpga_0_Generic_External_Memory_Mem_DQ_pin : inout std_logic_vector(0 to 15);
      fpga_0_Generic_External_Memory_MEM_CEFn_pin : out std_logic;
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_clk_pin : in std_logic;
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_clk_pin : in std_logic;
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_crs_pin : in std_logic;
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_dv_pin : in std_logic;
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_data_pin : in std_logic_vector(3 downto 0);
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_col_pin : in std_logic;
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_er_pin : in std_logic;
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rst_n_pin : out std_logic;
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_en_pin : out std_logic;
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_data_pin : out std_logic_vector(3 downto 0);
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_MDC_pin : out std_logic;
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_MDIO_pin : inout std_logic;
      fpga_0_Generic_SPI_SCK_pin : inout std_logic;
      fpga_0_Generic_SPI_MISO_pin : inout std_logic;
      fpga_0_Generic_SPI_MOSI_pin : inout std_logic;
      fpga_0_RS232_RX_pin : in std_logic;
      fpga_0_RS232_TX_pin : out std_logic;
      fpga_0_RS232_1_RX_pin : in std_logic;
      fpga_0_RS232_1_TX_pin : out std_logic;
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_pin : out std_logic;
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_n_pin : out std_logic;
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CE_pin : out std_logic;
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_n_pin : out std_logic;
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_ODT_pin : out std_logic;
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_RAS_n_pin : out std_logic;
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CAS_n_pin : out std_logic;
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_WE_n_pin : out std_logic;
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_BankAddr_pin : out std_logic_vector(1 downto 0);
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Addr_pin : out std_logic_vector(12 downto 0);
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQ_pin : inout std_logic_vector(63 downto 0);
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DM_pin : out std_logic_vector(7 downto 0);
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_pin : inout std_logic_vector(7 downto 0);
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_n_pin : inout std_logic_vector(7 downto 0);
      fpga_0_clk_1_sys_clk_pin : in std_logic;
      fpga_0_rst_1_sys_rst_pin : in std_logic
    );
  end component;

  -- Internal signals

  signal fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_MDC_pin : std_logic;
  signal fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_MDIO_pin : std_logic;
  signal fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_col_pin : std_logic;
  signal fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_crs_pin : std_logic;
  signal fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_dv_pin : std_logic;
  signal fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rst_n_pin : std_logic;
  signal fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_clk_pin : std_logic;
  signal fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_data_pin : std_logic_vector(3 downto 0);
  signal fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_er_pin : std_logic;
  signal fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_clk_pin : std_logic;
  signal fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_data_pin : std_logic_vector(3 downto 0);
  signal fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_en_pin : std_logic;
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Addr_pin : std_logic_vector(12 downto 0);
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_BankAddr_pin : std_logic_vector(1 downto 0);
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CAS_n_pin : std_logic;
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CE_pin : std_logic;
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_n_pin : std_logic;
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_n_pin : std_logic;
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_pin : std_logic;
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DM_pin : std_logic_vector(7 downto 0);
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_n_pin : std_logic_vector(7 downto 0);
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_pin : std_logic_vector(7 downto 0);
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQ_pin : std_logic_vector(63 downto 0);
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_ODT_pin : std_logic;
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_RAS_n_pin : std_logic;
  signal fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_WE_n_pin : std_logic;
  signal fpga_0_Generic_External_Memory_MEM_CEFn_pin : std_logic;
  signal fpga_0_Generic_External_Memory_Mem_A_pin : std_logic_vector(0 to 31);
  signal fpga_0_Generic_External_Memory_Mem_BEN_pin : std_logic_vector(0 to 1);
  signal fpga_0_Generic_External_Memory_Mem_CEN_pin : std_logic;
  signal fpga_0_Generic_External_Memory_Mem_DQ_pin : std_logic_vector(0 to 15);
  signal fpga_0_Generic_External_Memory_Mem_OEN_pin : std_logic;
  signal fpga_0_Generic_External_Memory_Mem_RPN_pin : std_logic;
  signal fpga_0_Generic_External_Memory_Mem_WEN_pin : std_logic;
  signal fpga_0_Generic_SPI_MISO_pin : std_logic;
  signal fpga_0_Generic_SPI_MOSI_pin : std_logic;
  signal fpga_0_Generic_SPI_SCK_pin : std_logic;
  signal fpga_0_RS232_1_RX_pin : std_logic;
  signal fpga_0_RS232_1_TX_pin : std_logic;
  signal fpga_0_RS232_RX_pin : std_logic;
  signal fpga_0_RS232_TX_pin : std_logic;
  signal fpga_0_clk_1_sys_clk_pin : std_logic;
  signal fpga_0_rst_1_sys_rst_pin : std_logic;

  -- START USER CODE (Do not remove this line)

  -- User: Put your signals here. Code in this
  --       section will not be overwritten.

  -- END USER CODE (Do not remove this line)

begin

  dut : system
    port map (
      fpga_0_Generic_External_Memory_Mem_A_pin => fpga_0_Generic_External_Memory_Mem_A_pin,
      fpga_0_Generic_External_Memory_Mem_RPN_pin => fpga_0_Generic_External_Memory_Mem_RPN_pin,
      fpga_0_Generic_External_Memory_Mem_CEN_pin => fpga_0_Generic_External_Memory_Mem_CEN_pin,
      fpga_0_Generic_External_Memory_Mem_OEN_pin => fpga_0_Generic_External_Memory_Mem_OEN_pin,
      fpga_0_Generic_External_Memory_Mem_WEN_pin => fpga_0_Generic_External_Memory_Mem_WEN_pin,
      fpga_0_Generic_External_Memory_Mem_BEN_pin => fpga_0_Generic_External_Memory_Mem_BEN_pin,
      fpga_0_Generic_External_Memory_Mem_DQ_pin => fpga_0_Generic_External_Memory_Mem_DQ_pin,
      fpga_0_Generic_External_Memory_MEM_CEFn_pin => fpga_0_Generic_External_Memory_MEM_CEFn_pin,
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_clk_pin => fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_clk_pin,
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_clk_pin => fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_clk_pin,
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_crs_pin => fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_crs_pin,
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_dv_pin => fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_dv_pin,
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_data_pin => fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_data_pin,
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_col_pin => fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_col_pin,
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_er_pin => fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_er_pin,
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rst_n_pin => fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rst_n_pin,
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_en_pin => fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_en_pin,
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_data_pin => fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_data_pin,
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_MDC_pin => fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_MDC_pin,
      fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_MDIO_pin => fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_MDIO_pin,
      fpga_0_Generic_SPI_SCK_pin => fpga_0_Generic_SPI_SCK_pin,
      fpga_0_Generic_SPI_MISO_pin => fpga_0_Generic_SPI_MISO_pin,
      fpga_0_Generic_SPI_MOSI_pin => fpga_0_Generic_SPI_MOSI_pin,
      fpga_0_RS232_RX_pin => fpga_0_RS232_RX_pin,
      fpga_0_RS232_TX_pin => fpga_0_RS232_TX_pin,
      fpga_0_RS232_1_RX_pin => fpga_0_RS232_1_RX_pin,
      fpga_0_RS232_1_TX_pin => fpga_0_RS232_1_TX_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_n_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_n_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CE_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CE_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_n_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_n_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_ODT_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_ODT_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_RAS_n_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_RAS_n_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CAS_n_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CAS_n_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_WE_n_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_WE_n_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_BankAddr_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_BankAddr_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Addr_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Addr_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQ_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQ_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DM_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DM_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_pin,
      fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_n_pin => fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_n_pin,
      fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin,
      fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin
    );

  -- Clock generator for fpga_0_clk_1_sys_clk_pin

  process
  begin
    fpga_0_clk_1_sys_clk_pin <= '0';
    loop
      wait for (fpga_0_clk_1_sys_clk_pin_PERIOD/2);
      fpga_0_clk_1_sys_clk_pin <= not fpga_0_clk_1_sys_clk_pin;
    end loop;
  end process;

  -- Reset Generator for fpga_0_rst_1_sys_rst_pin

  process
  begin
    fpga_0_rst_1_sys_rst_pin <= '1';
    wait for (fpga_0_rst_1_sys_rst_pin_LENGTH);
    fpga_0_rst_1_sys_rst_pin <= not fpga_0_rst_1_sys_rst_pin;
    wait;
  end process;

  -- START USER CODE (Do not remove this line)

  -- User: Put your stimulus here. Code in this
  --       section will not be overwritten.

  -- END USER CODE (Do not remove this line)

end architecture STRUCTURE;