--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
--Date        : Thu Feb 11 16:30:52 2016
--Host        : XKRHYUKK32 running 64-bit Service Pack 1  (build 7601)
--Command     : generate_target design_1_wrapper.bd
--Design      : design_1_wrapper
--Purpose     : IP block netlist
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
  port (
    clk_in1 : in STD_LOGIC;
    ext_reset_in : in STD_LOGIC;
    gpio_out : out STD_LOGIC_VECTOR ( 3 downto 0 )
  );
end design_1_wrapper;

architecture STRUCTURE of design_1_wrapper is
  component design_1 is
  port (
    clk_in1 : in STD_LOGIC;
    gpio_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ext_reset_in : in STD_LOGIC
  );
  end component design_1;
begin
design_1_i: component design_1
     port map (
      clk_in1 => clk_in1,
      ext_reset_in => ext_reset_in,
      gpio_out(3 downto 0) => gpio_out(3 downto 0)
    );
end STRUCTURE;