PARAMETER VERSION = 2.1.0


 PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
 PORT processing_system7_0_PS_SRSTB_pin = processing_system7_0_PS_SRSTB, DIR = I
 PORT processing_system7_0_PS_CLK_pin = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK
 PORT processing_system7_0_PS_PORB_pin = processing_system7_0_PS_PORB, DIR = I
 PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
 PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
 PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
 PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
 PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O
 PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
 PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
 PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
 PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
 PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
 PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
 PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO
 PORT rd_fifo_data = rx_npi_rd_fifo_data, DIR = O, VEC = [31:0]
 PORT rd_fifo_empty = rx_npi_rd_fifo_empty, DIR = O
 PORT rd_fifo_rd_en = rx_npi_rd_fifo_rd_en, DIR = I
 PORT rd_fifo_ready = rx_npi_rd_fifo_ready, DIR = O
 PORT rd_fifo_clk = rx_npi_rd_fifo_clk, DIR = I
 PORT rd_fifo_full = rx_npi_rd_fifo_full, DIR = O
 PORT wr_fifo_full = tx_npi_wr_fifo_full, DIR = O
 PORT wr_fifo_wr_en = tx_npi_wr_fifo_wr_en, DIR = I
 PORT wr_fifo_clk = tx_npi_wr_fifo_clk, DIR = I
 PORT wr_fifo_ready = tx_npi_wr_fifo_ready, DIR = O
 PORT wr_fifo_data = tx_npi_wr_fifo_data, DIR = I, VEC = [31:0]
 PORT wr_fifo_empty = tx_npi_wr_fifo_empty, DIR = O
 PORT clk_50mhz = processing_system7_0_FCLK_CLK0, DIR = O


BEGIN processing_system7
 PARAMETER INSTANCE = processing_system7_0
 PARAMETER HW_VER = 4.02.a
 PARAMETER C_DDR_RAM_HIGHADDR = 0x3FFFFFFF
 PARAMETER C_EN_EMIO_CAN0 = 0
 PARAMETER C_EN_EMIO_CAN1 = 0
 PARAMETER C_EN_EMIO_ENET0 = 0
 PARAMETER C_EN_EMIO_ENET1 = 0
 PARAMETER C_EN_EMIO_I2C0 = 0
 PARAMETER C_EN_EMIO_I2C1 = 0
 PARAMETER C_EN_EMIO_PJTAG = 0
 PARAMETER C_EN_EMIO_SDIO0 = 0
 PARAMETER C_EN_EMIO_CD_SDIO0 = 0
 PARAMETER C_EN_EMIO_WP_SDIO0 = 0
 PARAMETER C_EN_EMIO_SDIO1 = 0
 PARAMETER C_EN_EMIO_CD_SDIO1 = 0
 PARAMETER C_EN_EMIO_WP_SDIO1 = 0
 PARAMETER C_EN_EMIO_SPI0 = 0
 PARAMETER C_EN_EMIO_SPI1 = 0
 PARAMETER C_EN_EMIO_SRAM_INT = 0
 PARAMETER C_EN_EMIO_TRACE = 0
 PARAMETER C_EN_EMIO_TTC0 = 1
 PARAMETER C_EN_EMIO_TTC1 = 0
 PARAMETER C_EN_EMIO_UART0 = 0
 PARAMETER C_EN_EMIO_UART1 = 0
 PARAMETER C_EN_EMIO_MODEM_UART0 = 0
 PARAMETER C_EN_EMIO_MODEM_UART1 = 0
 PARAMETER C_EN_EMIO_WDT = 1
 PARAMETER C_EN_QSPI = 1
 PARAMETER C_EN_SMC = 0
 PARAMETER C_EN_CAN0 = 1
 PARAMETER C_EN_CAN1 = 0
 PARAMETER C_EN_ENET0 = 1
 PARAMETER C_EN_ENET1 = 0
 PARAMETER C_EN_I2C0 = 1
 PARAMETER C_EN_I2C1 = 0
 PARAMETER C_EN_PJTAG = 0
 PARAMETER C_EN_SDIO0 = 1
 PARAMETER C_EN_SDIO1 = 0
 PARAMETER C_EN_SPI0 = 0
 PARAMETER C_EN_SPI1 = 0
 PARAMETER C_EN_TRACE = 0
 PARAMETER C_EN_TTC0 = 1
 PARAMETER C_EN_TTC1 = 0
 PARAMETER C_EN_UART0 = 0
 PARAMETER C_EN_UART1 = 1
 PARAMETER C_EN_MODEM_UART0 = 0
 PARAMETER C_EN_MODEM_UART1 = 0
 PARAMETER C_EN_USB0 = 1
 PARAMETER C_EN_USB1 = 0
 PARAMETER C_EN_WDT = 1
 PARAMETER C_EN_DDR = 1
 PARAMETER C_EN_GPIO = 1
 PARAMETER C_FCLK_CLK0_FREQ = 50000000
 PARAMETER C_FCLK_CLK1_FREQ = 50000000
 PARAMETER C_FCLK_CLK2_FREQ = 50000000
 PARAMETER C_FCLK_CLK3_FREQ = 50000000
 PARAMETER C_USE_CR_FABRIC = 1
 PARAMETER C_USE_M_AXI_GP0 = 1
 PARAMETER C_USE_S_AXI_HP0 = 1
 PARAMETER C_INTERCONNECT_S_AXI_HP0_MASTERS = rx_npi.M_AXI & tx_npi.M_AXI
 PARAMETER C_PS7_SI_REV = PRODUCTION
 PARAMETER C_S_AXI_HP0_DATA_WIDTH = 32
 PARAMETER C_EMIO_GPIO_WIDTH = 64
 BUS_INTERFACE M_AXI_GP0 = axi4lite
 BUS_INTERFACE S_AXI_HP0 = axi4full
 PORT MIO = processing_system7_0_MIO
 PORT PS_SRSTB = processing_system7_0_PS_SRSTB
 PORT PS_CLK = processing_system7_0_PS_CLK
 PORT PS_PORB = processing_system7_0_PS_PORB
 PORT DDR_Clk = processing_system7_0_DDR_Clk
 PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
 PORT DDR_CKE = processing_system7_0_DDR_CKE
 PORT DDR_CS_n = processing_system7_0_DDR_CS_n
 PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
 PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
 PORT DDR_WEB = processing_system7_0_DDR_WEB
 PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
 PORT DDR_Addr = processing_system7_0_DDR_Addr
 PORT DDR_ODT = processing_system7_0_DDR_ODT
 PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
 PORT DDR_DQ = processing_system7_0_DDR_DQ
 PORT DDR_DM = processing_system7_0_DDR_DM
 PORT DDR_DQS = processing_system7_0_DDR_DQS
 PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
 PORT DDR_VRN = processing_system7_0_DDR_VRN
 PORT DDR_VRP = processing_system7_0_DDR_VRP
 PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0
 PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N
 PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK0
 PORT S_AXI_HP0_ACLK = processing_system7_0_FCLK_CLK0
 PORT IRQ_F2P = tx_npi_wr_fifo_interrupt & rx_npi_rd_fifo_interrupt
END

BEGIN axi_user_npi
 PARAMETER INSTANCE = tx_npi
 PARAMETER HW_VER = 4.00.b
 PARAMETER C_BASEADDR = 0x75c00000
 PARAMETER C_HIGHADDR = 0x75c0ffff
 BUS_INTERFACE M_AXI = axi4full
 BUS_INTERFACE S_AXI = axi4lite
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
 PORT m_axi_aclk = processing_system7_0_FCLK_CLK0
 PORT wr_fifo_interrupt = tx_npi_wr_fifo_interrupt
 PORT wr_fifo_full = tx_npi_wr_fifo_full
 PORT wr_fifo_wr_en = tx_npi_wr_fifo_wr_en
 PORT wr_fifo_clk = tx_npi_wr_fifo_clk
 PORT wr_fifo_ready = tx_npi_wr_fifo_ready
 PORT wr_fifo_data = tx_npi_wr_fifo_data
 PORT wr_fifo_empty = tx_npi_wr_fifo_empty
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
 PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4full
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 1
 PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
 PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END

BEGIN axi_user_npi
 PARAMETER INSTANCE = rx_npi
 PARAMETER HW_VER = 4.00.b
 PARAMETER C_BASEADDR = 0x75c20000
 PARAMETER C_HIGHADDR = 0x75c2ffff
 BUS_INTERFACE M_AXI = axi4full
 BUS_INTERFACE S_AXI = axi4lite
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
 PORT m_axi_aclk = processing_system7_0_FCLK_CLK0
 PORT rd_fifo_interrupt = rx_npi_rd_fifo_interrupt
 PORT rd_fifo_data = rx_npi_rd_fifo_data
 PORT rd_fifo_empty = rx_npi_rd_fifo_empty
 PORT rd_fifo_rd_en = rx_npi_rd_fifo_rd_en
 PORT rd_fifo_ready = rx_npi_rd_fifo_ready
 PORT rd_fifo_clk = rx_npi_rd_fifo_clk
 PORT rd_fifo_full = rx_npi_rd_fifo_full
END

BEGIN chipscope_axi_monitor
 PARAMETER INSTANCE = chipscope_axi_monitor_0
 PARAMETER HW_VER = 3.05.a
 PARAMETER C_MAX_SEQUENCER_LEVELS = 2
 PARAMETER C_USE_INTERFACE = 0
 PARAMETER C_NUM_DATA_SAMPLES = 1024
 BUS_INTERFACE MON_AXI = processing_system7_0.S_AXI_HP0
 PORT chipscope_icon_control = chipscope_axi_monitor_0_icon_ctrl
END

BEGIN chipscope_icon
 PARAMETER INSTANCE = chipscope_icon_0
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_NUM_CONTROL_PORTS = 1
 PORT control0 = chipscope_axi_monitor_0_icon_ctrl
END