-------------------------------------------------------------------------------
-- system_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity system_top is
  port (
    RS232_Uart_1_sout : out std_logic;
    RS232_Uart_1_sin : in std_logic;
    RESET : in std_logic;
    CLK_P : in std_logic;
    CLK_N : in std_logic;
    axi_uartlite_0_RX_pin : in std_logic;
    axi_uartlite_0_TX_pin : out std_logic
   );
end system_top;

architecture STRUCTURE of system_top is

  component system is
    port (
      RS232_Uart_1_sout : out std_logic;
      RS232_Uart_1_sin : in std_logic;
      RESET : in std_logic;
      CLK_P : in std_logic;
      CLK_N : in std_logic;
      axi_uartlite_0_RX_pin : in std_logic;
      axi_uartlite_0_TX_pin : out std_logic;
      bram_add_0 : out std_logic_vector(10 downto 0);
      bram_we_0 : out std_logic_vector(3 downto 0);
      bram_clk_0 : out std_logic;
      bram_cs_0 : out std_logic;
      bram_din_0 : out std_logic_vector(31 downto 0);
      bram_dout_0 : in std_logic_vector(31 downto 0);
      bram_cs_1 : out std_logic;
      bram_we_1 : out std_logic_vector(3 downto 0);
      bram_dout_1 : in std_logic_vector(31 downto 0);
      bram_add_1 : out std_logic_vector(10 downto 0);
      bram_clk_1 : out std_logic;
      bram_din_1 : out std_logic_vector(31 downto 0)
    );
  end component;

  attribute BOX_TYPE : STRING;
  attribute BOX_TYPE of system : component is "user_black_box";
	  
 COMPONENT bram_8k
  PORT (
    clka : IN STD_LOGIC;
    ena : IN STD_LOGIC;
    wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    clkb : IN STD_LOGIC;
    enb : IN STD_LOGIC;
    web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
    dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
END COMPONENT;
   signal bram_we_0,bram_we_1  :  std_logic_vector(3 downto 0);
   signal bram_add_0, bram_add_1 :  std_logic_vector(10 downto 0);
   signal bram_be_0, bram_be_1 :  std_logic_vector(3 downto 0);
   signal bram_clk_0, bram_clk_1 :  std_logic;
   signal bram_cs_0, bram_cs_1 :  std_logic;
   signal bram_din_0, bram_din_1 :  std_logic_vector(31 downto 0);
   signal bram_dout_0, bram_dout_1:  std_logic_vector(31 downto 0);

begin

  system_i : system
    port map (
      RS232_Uart_1_sout => RS232_Uart_1_sout,
      RS232_Uart_1_sin => RS232_Uart_1_sin,
      RESET => RESET,
      CLK_P => CLK_P,
      CLK_N => CLK_N,
      axi_uartlite_0_RX_pin => axi_uartlite_0_RX_pin,
      axi_uartlite_0_TX_pin => axi_uartlite_0_TX_pin,
      bram_we_0 => bram_we_0,
      bram_add_0 => bram_add_0,
      bram_clk_0 => bram_clk_0,
      bram_cs_0 => bram_cs_0,
      bram_din_0 => bram_din_0,
      bram_dout_0 => bram_dout_0,
      bram_cs_1 => bram_cs_1,
      bram_dout_1 => bram_dout_1,
      bram_add_1 => bram_add_1,
      bram_clk_1 => bram_clk_1,
      bram_we_1 => bram_we_1,
      bram_din_1 => bram_din_1
    );

  bram_8k_0 : bram_8k
  PORT MAP (
    clka => bram_clk_0,
    ena => bram_cs_0,
    wea => bram_we_0,
    addra => bram_add_0,
    dina => bram_din_0,
    douta => bram_dout_0,
    clkb => bram_clk_1,
    enb => bram_cs_1,
    web => bram_we_1,
    addrb => bram_add_1,
    dinb => bram_din_1,
    doutb => bram_dout_1
  );
end architecture STRUCTURE;